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US 12,702,019 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsKanggyune Lee, Sangwon Lee, Woojin Choi
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a package substrate, a first semiconductor chip on the package substrate, a sealing layer on the package substrate and at least partially covering the first semiconductor chip and including an upper surface, a first side surface, and a first inclined surface extending between the upper surface and the first side surface, and a first marking pattern in or on the first inclined surface of the sealing layer.
Claims20
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip on the package substrate;
- a sealing layer on the package substrate and at least partially covering the first semiconductor chip, the sealing layer comprising an upper surface extending in a first direction, a first side surface that extends in a second direction transverse to the first direction, and a first inclined surface having a first portion and a second portion, each of the first portion and the second portion extending between and in a third direction transverse to the upper surface and the first side surface;
- and
- a first information marking pattern in or on the first portion of the first inclined surface of the sealing layer,
- wherein no information marking pattern is in or on the second portion of the first inclined surface of the sealing layer.
3 more elements
A semiconductor package comprising:
- a package substrate;
- a chip structure on an upper surface of the package substrate and comprising a plurality of semiconductor chips stacked in a first direction that is perpendicular to the upper surface of the package substrate;
- a sealing layer on the package substrate and at least partially covering the chip structure, the sealing layer comprising an upper surface extending in a second direction, a first side surface that extends in the first direction transverse to the second direction, and a first inclined surface extending between and transverse to the upper surface and the first side surface;
- and
- a first marking pattern in or on the first inclined surface of the sealing layer, the first marking pattern having a portion that is in or on the first inclined surface and overlies and is aligned with at least one of the plurality of semiconductor chips in the first direction,
- wherein a distance in a first lateral direction between a first one of the plurality of semiconductor chips and the first side surface of the sealing layer is greater than a distance in the first lateral direction between a lower second one of the plurality of semiconductor chips and the first side surface of the sealing layer.
3 more elements
A semiconductor package comprising:
- a package substrate;
- a chip structure on an upper surface of the package substrate and comprising a plurality of semiconductor chips stacked in a first direction that is perpendicular to the upper surface of the package substrate;
- a sealing layer on the package substrate and at least partially covering the chip structure, the sealing layer comprising an upper surface extending in a second direction, a first side surface that extends in the first direction transverse to the second direction, a second side surface, a first inclined surface having a first portion and a second portion, each of the first portion and the second portion extending between and in a third direction transverse to the upper surface and the first side surface, and a second inclined surface extending between the upper surface and the second side surface;
- a first information marking pattern in or on the first portion of the first inclined surface of the sealing layer and overlying at least one of the plurality of semiconductor chips in the first direction;
- and
- a second marking pattern in or on the second inclined surface of the sealing layer and overlying at least one of the plurality of semiconductor chips,
- wherein the first inclined surface of the sealing layer and the second inclined surface of the sealing layer are connected to each other,
- wherein a distance in a first lateral direction between a first one of the plurality of semiconductor chips and the first side surface of the sealing layer is greater than a distance in the first lateral direction between a lower second one of the plurality of semiconductor chips and the first side surface of the sealing layer,
- wherein a distance in a second lateral direction between the first one of the plurality of semiconductor chips and the second side surface of the sealing layer is greater than a distance in the second lateral direction between the second one of the plurality of semiconductor chips and the second side surface of the sealing layer, and
- wherein no information marking pattern is in or on the second portion of the first inclined surface of the sealing layer.
7 more elements
Dependencies are inferred from the claim text.