Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsJingu Kim, Taesung Jeong, Doohwan Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes: a first redistribution layer including a first wiring; a die located on the first redistribution layer; and a shielding structure surrounding the die from an upper surface and side surfaces of the die, wherein the shielding structure includes: a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die.
Claims19
A semiconductor package comprising:
- a first redistribution layer including a first wiring;
- a die located on the first redistribution layer;
- a shielding structure surrounding an upper surface and side surfaces of the die;
- and
- a plurality of posts disposed outside the shielding structure on the first redistribution layer, and electrically connected to the first wiring,
- wherein the shielding structure comprises:
- a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die;
- and
- a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die,
- wherein upper surfaces of the shielding wall and the plurality of posts are coplanar with each other, and
- wherein the shielding cover contacts the upper surface of the shielding wall.
A semiconductor package comprising:
- a first redistribution layer including a first wiring;
- a die located on the first redistribution layer;
- a bump located between the first redistribution layer and the die and electrically connecting the die to the first wiring;
- a shielding structure comprising a shielding wall that is spaced apart from side surfaces of the die and surrounds four sides of the die and a shielding cover which is spaced apart from an upper surface of the die and also surrounds the upper surface of the die, and has a flat lower surface, the shielding structure surrounding the die from the upper surface and the side surfaces of the die;
- a plurality of posts located on the first redistribution layer and outside the shielding wall to be spaced apart from the shielding structure, the plurality of posts being electrically connected to the first wiring;
- a molding member surrounding the die, the shielding wall, and the plurality of posts, and filling a space between the die, the shielding wall, and the plurality of posts;
- a second redistribution layer which is located on the shielding wall, the shielding cover, and the plurality of posts, includes a second wiring, and is electrically connected to the shielding wall and the plurality of posts through the second wiring;
- and
- an external connection terminal attached below the first redistribution layer,
- wherein upper surfaces of the shielding wall and upper surfaces of the plurality of posts are coplanar with each other, and
- wherein the shielding cover contacts the upper surface of the shielding wall.
A semiconductor package comprising:
- a first redistribution layer including a first wiring;
- a die disposed on the first redistribution layer;
- a shielding structure comprising a shielding wall that is spaced apart from side surfaces of the die and extends to continuously surround the side surfaces of the die, and a shielding cover that is spaced apart from an upper surface of the die and vertically overlaps the side surfaces of the die;
- and
- a plurality of posts disposed on the first redistribution layer to be spaced apart from the shielding structure, the plurality of posts being electrically connected to the first wiring,
- wherein the shielding wall is between the plurality of posts and the die,
- wherein upper surfaces of the shielding wall and the plurality of posts are coplanar with each other, and
- wherein the shielding cover contacts the upper surface of the shielding wall.
Dependencies are inferred from the claim text.