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US 12,701,991 B2Granted
Integrated isolation capacitor with enhanced bottom plate
AssigneeTexas Instruments Incorporated
InventorsByron Lovell Williams, Elizabeth Costner Stewart, Jeffrey Alan West, Thomas Dyer Bonifield
Life of this patent
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Abstract
An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 μm to 6.0 μm, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 μm to 1.0 μm.
Claims24
An electronic device, comprising:
- a multilevel metallization structure over a semiconductor layer, the multilevel metallization structure having a first region, a second region, a pre-metal level over the semiconductor layer, and metallization structure levels over the pre-metal level, the pre-metal level and the metallization structure levels extending in respective planes of orthogonal first and second directions and arranged in a stack along a third direction that is orthogonal to the first and second directions, and the metallization structure levels including a first metallization structure level and a second metallization structure level;
- a capacitor in the first region of the multilevel metallization structure, the capacitor having a first terminal and a second terminal, the first terminal forming a first capacitor plate in the first metallization structure level, the second terminal forming a second capacitor plate in the second metallization structure level, and the first terminal overlapping the second terminal by an overlap distance in the first and second directions, the overlap distance being 1.0 μm to 6.0 μm;
- and
- a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield having interconnected metal lines and vias in the respective metallization structure levels that at least partially encircle the first region of the multilevel metallization structure, the conductive shield electrically connected to the semiconductor layer, the conductive shield including a first metal line that encircles the first terminal in the first metallization structure level, the first metal line spaced apart from the first terminal by a gap distance in the first and second directions, the gap distance being at least 0.5 μm and less than 1.0 μm.
1 more element
A packaged electronic device, comprising:
- a semiconductor die, including:
- a semiconductor layer;
- a multilevel metallization structure over the semiconductor layer, the multilevel metallization structure having a first region, a second region, a pre-metal level on the semiconductor layer, and metallization structure levels over the pre-metal level, the pre-metal level and the metallization structure levels extending in respective planes of orthogonal first and second directions and arranged in a stack along a third direction that is orthogonal to the first and second directions, and the metallization structure levels including a first metallization structure level and a second metallization structure level;
- a capacitor in the first region of the multilevel metallization structure, the capacitor having a first terminal and a second terminal, the first terminal forming a first capacitor plate in the first metallization structure level, the second terminal forming a second capacitor plate in the second metallization structure level;
- and, the first terminal overlapping the second terminal by an overlap distance in the first and second directions, the overlap distance being 1.0 μm to 6.0 μm, the second terminal including an exposed side;
- and
- a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield having interconnected metal lines and vias in the respective metallization structure levels that at least partially encircle the first region of the multilevel metallization structure, the conductive shield coupled to the semiconductor layer, the conductive shield including a first metal line that encircles the first terminal in the first metallization structure level, the first metal line spaced apart from the first terminal by a gap distance in the first and second directions, the gap distance being at least 0.5 μm and less than 1.0 μm;
- an electrical connection including an end bonded to the exposed side of the second terminal;
- a package structure that encloses the semiconductor die and the electrical connection;
- and
- conductive leads exposed along one or more sides of the package structure.
8 more elements
A method of forming an integrated circuit, comprising:
- forming a multilevel metallization structure over a semiconductor layer, the multilevel metallization structure having:
- a first region;
- a second region;
- a capacitor in the first region;
- a pre-metal level on the semiconductor layer;
- metallization structure levels over the pre-metal level;
- and a conductive shield between the first region and the second region;
- the pre-metal level and the metallization structure levels extending in respective planes of orthogonal first and second directions and arranged in a stack along a third direction that is orthogonal to the first and second directions, and the metallization structure levels including a first metallization structure level and a second metallization structure level;
- the capacitor having a first terminal and a second terminal, the first terminal forming a first capacitor plate in the first metallization structure level, the second terminal forming a second capacitor plate in the second metallization structure level;
- the first terminal overlapping the second terminal by an overlap distance in the first and second directions, and the overlap distance being 1.0 μm to 6.0 μm;
- and the conductive shield having interconnected metal lines and vias in the respective metallization structure levels that at least partially encircle the first region of the multilevel metallization structure, the conductive shield coupled to the semiconductor layer, the conductive shield including a first metal line that encircles the first terminal in the first metallization structure level, the first metal line spaced apart from the first terminal by a gap distance in the first and second directions, and the gap distance being at least 0.5 μm and less than 1.0 μm;
- separating a semiconductor die including the semiconductor layer and the multilevel metallization structure from a wafer;
- forming an electrical connection to the second terminal of the capacitor;
- and
- enclosing the semiconductor die and the electrical connection in a package structure with conductive leads exposed along one or more sides of the package structure.
12 more elements
An integrated circuit, comprising:
- an upper capacitor plate in an upper metal level over a semiconductor substrate, and a lower capacitor plate in a lower metal level over semiconductor substrate, the upper capacitor plate overlapping the lower capacitor plate such that the lower capacitor plate completely extends laterally beyond the upper capacitor plate by an overlap distance in a range from 1.0 μm to 6.0 μm;
- and
- a ground ring in the lower metal level surrounding the lower capacitor plate, the ground ring and the lower capacitor plate being laterally spaced apart by a gap distance in a range from 0.5 μm to less than 1.0 μm.
Dependencies are inferred from the claim text.