Semiconductor device structure and manufacturing method thereof

A manufacturing method of a semiconductor device structure, comprising:

• providing a semiconductor substrate having through vias embedded therein;
• forming a device layer on a first side of the semiconductor substrate, wherein the device layer is formed with a plurality of transistors;
• forming a first material layer on a second side of the semiconductor substrate opposite to the first side and performing doping to the first material layer, wherein the first material layer is formed with first nano grains of a first grain size and contains first dopants;
• forming a first cap layer on the first material layer covering the first material layer;
• forming a first nanostructured material layer below the first cap layer by performing a first laser annealing process, wherein the first nanostructured material layer is formed with second nano grains of a second grain size that is larger than the first grain size, and the first dopants are distributed along grain boundaries of the second nano grains;
• forming first metallization structures in the first nanostructured material layer;
• forming a second material layer over the first material layer and performing doping to the second material layer, wherein the second material layer is formed with third nano grains of a third grain size and contains second dopants;
• forming a second cap layer on the second material layer covering the second material layer;
• forming a second nanostructured material layer below the second cap layer by performing a second laser annealing process, wherein the second material layer is formed with fourth nano grains of a fourth grain size that is larger than the third grain size, and the second dopants are distributed along grain boundaries of the fourth nano grains;
• and
• forming second metallization structures in the second nanostructured material layer.

A semiconductor device structure, comprising:

• a semiconductor substrate having a first surface and a second surface opposite to the first surface;
• a device layer disposed on the first surface of the semiconductor substrate, wherein the device layer includes a plurality of transistors;
• and
• backside connection structures, disposed on the second surface of the semiconductor substrate and electrically connected with the plurality of transistors,
• wherein the backside connection structures include backside metallization structures and at least one insulating nanostructured material having nano grains and dopants distributed along grain boundaries of the nano grains.