Integrated circuit devices including intergate spacer and methods of fabrication the same

An integrated circuit device comprising:

• an upper transistor on a substrate, the upper transistor comprising an upper channel region;
• a lower transistor between the substrate and the upper transistor, the lower transistor comprising a lower channel region and a lower work function layer on the lower channel region;
• an intergate spacer comprising an insulating material, wherein the lower work function layer is between the lower channel region and the intergate spacer;
• and
• a gate layer on the intergate spacer,
• wherein a lower surface of the upper channel region is closer than an upper surface of the intergate spacer to the substrate.

A method of forming an integrated circuit device, the method comprising:

• forming a lower stack and an upper stack on a substrate, wherein the lower stack is between the substrate and the upper stack, the lower stack comprises a lower sacrificial pattern and a lower channel region stacked in a vertical direction, and the upper stack comprises an upper sacrificial pattern and an upper channel region stacked in the vertical direction;
• forming a dummy gate insulator on the lower stack and the upper stack;
• forming an intergate spacer adjacent to a side surface of the lower stack;
• removing the dummy gate insulator, the lower sacrificial pattern and the upper sacrificial pattern, thereby exposing the lower channel region and the upper channel region and forming a cavity between the lower channel region and the intergate spacer;
• forming a gate insulator on the lower channel region and the upper channel region;
• forming a lower work function layer on the gate insulator and in the cavity between the lower channel region and the intergate spacer;
• forming an upper work function layer on the lower work function layer and the intergate spacer;
• and
• forming an upper gate layer on the upper work function layer.