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US 12,701,781 B2Granted
Integrated circuit with a gate structure and method making the same
AssigneeTaiwan Semconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Ying-Keung Leung, Chi On Chui
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Abstract
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.
Claims20
A device comprising:
- a first gate stack disposed on a substrate, the first gate stack including a first gate dielectric layer and a first gate electrode;
- a first spacer layer disposed on the first gate stack and interfacing with the first gate dielectric layer and a portion of the substrate, the portion of the substrate being adjacent the first gate dielectric layer and free of any source/drain feature;
- a second spacer layer disposed on the first spacer layer and formed of a different material than the first spacer layer;
- and
- a first dielectric layer disposed between the first spacer layer and the first gate dielectric layer such that the first dielectric layer interfaces with the first gate dielectric layer and the first spacer layer, wherein a first portion of the first gate dielectric layer extends under the first dielectric layer such that the first portion of the first gate dielectric layer is disposed between the substrate and the first dielectric layer, the first portion of the first gate dielectric layer having a first thickness, and wherein a second portion of the first gate dielectric layer extends under the first gate electrode, the second portion of the first gate dielectric layer having a second thickness that is less than the first thickness.
2 more elements
A device comprising:
- a first gate stack and a second gate stack disposed on a substrate;
- a first dielectric material layer disposed on a sidewall of the first gate stack with a first thickness, wherein the first dielectric material layer is formed of the same material throughout the first dielectric material layer;
- and
- a second dielectric material layer disposed on a sidewall of the second gate stack with a second thickness that is different than the first thickness, wherein the second dielectric material layer is formed of the same material throughout the second dielectric material layer, and
- wherein the first gate stack includes a first gate dielectric layer and a first gate electrode over the first gate dielectric layer, wherein a first portion of the first gate dielectric layer extends under the first dielectric material layer such that the first portion of the first gate dielectric layer is disposed between the substrate and the first dielectric material layer, wherein a second portion of the first gate dielectric layer is disposed between and interfaces with a sidewall of the first gate electrode and a sidewall of the first dielectric material layer, wherein the first dielectric material layer physically contacts the first gate dielectric layer, and
- wherein the second gate stack includes a second gate dielectric layer and a second electrode over the second gate dielectric layer, the second gate dielectric layer having a different thickness than that of the first gate dielectric layer, wherein a first portion of the second gate dielectric layer extends under the second dielectric material layer such that the first portion of the second gate dielectric layer is disposed between the substrate and the second dielectric material layer, wherein a second portion of the second gate dielectric layer is disposed between and interfaces with a sidewall of the second gate electrode and a sidewall of the second dielectric material layer, wherein the second dielectric material layer physically contacts the second gate dielectric layer.
3 more elements
A device comprising:
- a first gate stack disposed over a substrate, the first gate stack extending to a first height above the substrate;
- a first gate spacer disposed along an entire length of a first sidewall of the first gate stack such that the first gate spacer does not extend beyond the first height above the substrate, wherein a bottom surface of the first gate spacer interfaces the substrate;
- a first dielectric material layer disposed along a first portion of the first sidewall of the first gate stack without being disposed along a second portion of the first sidewall, wherein the first dielectric material layer physically contacts the first gate spacer and the first portion of the first sidewall of the first gate stack;
- a second gate stack disposed over a substrate;
- a second gate spacer disposed along an entire length of a second sidewall of the second gate stack;
- and
- a second dielectric material layer disposed along a first portion of the second sidewall of the second gate stack without being disposed along a second portion of the second sidewall,
- wherein the second dielectric material layer physically contacts the second gate spacer and the first portion of the second sidewall of the second gate stack,
- wherein the first gate stack includes a first gate dielectric layer and a first gate electrode over the first gate dielectric layer,
- wherein the second gate stack includes a second gate dielectric layer and a second gate electrode over the second gate dielectric layer,
- wherein the second gate dielectric layer does not extend between a bottom surface of the second spacer and the substrate,
- wherein a portion of the first gate dielectric layer is sandwiched between a sidewall portion of the first dielectric material layer and a sidewall of the first gate electrode,
- wherein a portion of the second gate dielectric layer is sandwiched between a sidewall portion of the second dielectric material layer and a sidewall of the second gate electrode.
10 more elements
Dependencies are inferred from the claim text.