Semiconductor structure and method for manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsZhi-Ren Xiao, Nuo Xu, Chih-Ching Wang, Jon-Hsu Ho, Chung-Wei Wu, Zhiqiang Wu
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a substrate, nanostructures, source/drain features, a gate structure, and inner spacers. The nanostructures are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are electrically connected to and on opposite sides of the nanostructures in an X-direction. The gate structure extends in a Y-direction and wraps around the nanostructures. The inner spacers are between the nanostructures in the Z-direction. Each of the inner spacers includes a soft core layer and a hard liner layer wrapping around the soft core layer.
Claims20
A semiconductor structure, comprising:
- a substrate;
- nanostructures over the substrate and spaced apart from each other in a Z-direction;
- source/drain features electrically connected to and on opposite sides of the nanostructures in an X-direction;
- a gate structure extending in a Y-direction and wrapping around the nanostructures;
- and
- inner spacers between the nanostructures in the Z-direction, wherein each of the inner spacers comprises:
- a soft core layer;
- and
- a hard liner layer wrapping around the soft core layer.
A semiconductor structure, comprising:
- a substrate;
- nanostructures over the substrate and spaced apart from each other in a Z-direction;
- a gate structure extending in a Y-direction and wrapping around middle portions of the nanostructures;
- source/drain features on opposite sides of the gate structure in an X-direction and attached to the nanostructures in the X-direction;
- and
- inner spacers between side portions of the nanostructures in the Z-direction, wherein each of the inner spacers comprises:
- a soft core layer;
- and
- a hard liner layer wrapping around the soft core layer, wherein the hard liner layers separate the core layers from the nanostructures, the gate structure, and the source/drain features.
A method for manufacturing a semiconductor structure, comprising:
- forming a fin over a substrate, wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked in a Z-direction;
- forming a dummy gate structure extending in a Y-direction and over the fin;
- forming gate spacers on sidewalls of the dummy gate structure in an X-direction;
- forming source/drain trenches in the fin and on opposite sides of the dummy gate structures in the X-direction;
- removing side portions of the first semiconductor layers through the source/drain trenches to form gaps between the second semiconductor layers in the Z-direction and direct under the gate spacers;
- forming first liner layers partially filling the gaps;
- forming core layers partially filling spaces in the gaps and the first liner layers;
- forming second liner layers filling remaining spaces in the gaps;
- forming P-type source/drain features in the source/drain trenches;
- and
- replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the second semiconductor layers.
Dependencies are inferred from the claim text.