Superjunction silicon carbide semiconductor device having trench gate structures formed on stacked layers of parallel pn junctions extending in different directions and method thereof

A superjunction silicon carbide semiconductor device, comprising:

• a silicon carbide semiconductor substrate of a first conductivity type, having a front surface and a back surface opposite to the front surface;
• a first semiconductor layer of the first conductivity type, provided on the front surface of the substrate, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the substrate;
• a lower parallel pn structure provided at a surface of the first semiconductor layer, having a first surface and a second surface that are opposite to each other and parallel to the front surface of the substrate, and including a plurality of lower first columns of the first conductivity type and a plurality of lower second columns of a second conductivity type that are disposed repeatedly alternating with each other to form a stripe pattern on the second surface thereof, the lower first columns and the lower second columns extending in a first direction;
• an upper parallel pn structure provided on the first surface of the lower parallel pn structure, having a first surface and a second surface that are opposite to each other and parallel to the front surface of the substrate, and including a plurality of upper first columns of the first conductivity type and a plurality of upper second columns of the second conductivity type that are disposed repeatedly alternating with each other to form a stripe pattern on the second surface thereof, the upper first columns and the upper second columns extending in a second direction different than the first direction;
• a second semiconductor layer of the second conductivity type, provided on a surface of the upper parallel pn structure;
• a first semiconductor region of the first conductivity type, selectively provided in a surface layer of the second semiconductor layer;
• a plurality of trenches, each of which penetrates the first semiconductor region and the second semiconductor layer, and reaches the upper parallel pn structure;
• a plurality of gate electrodes, each of which is provided in a corresponding one of the trenches via a gate insulating film;
• an interlayer insulating film provided on the gate electrodes;
• a first electrode in contact with the second semiconductor layer and the first semiconductor region;
• and
• a second electrode provided at the back surface of the substrate, wherein
• at the second surface of the upper parallel pn structure, in a direction orthogonal to the second direction, an arithmetic product of a width and an impurity concentration of each of the plurality of upper first columns and an arithmetic product of a width and an impurity concentration of each of the plurality of upper second columns differ by no more than 5% of each other, whereby the upper parallel pn structure is charge balanced as the superjunction silicon carbide semiconductor device,
• an impurity concentration of the upper first columns is lower than an impurity concentration of the first semiconductor region and higher than the impurity concentration of the first semiconductor layer,
• a bottom of each of the plurality of trenches is embedded in a corresponding one of the plurality of upper second columns, and
• the impurity concentration of each of the plurality of upper second columns and an impurity concentration of each of the plurality of lower second columns are higher than an impurity concentration of the second semiconductor layer.