Doping profile for strained source/drain region

An integrated chip, comprising:

• a substrate;
• a gate structure disposed over an upper surface of the substrate;
• source/drain regions arranged along opposing sides of the gate structure;
• a channel region disposed vertically below the gate structure and laterally between the source/drain regions, wherein the source/drain regions respectively have a strain inducing component concentration profile that decreases from a first value to a lower second value at a first gradient and that decreases from the second value to a third value at a second gradient;
• wherein the first gradient does not equal the second gradient;
• and
• wherein the first value is a smaller vertical distance from the upper surface of the substrate than the second value, and the second value is a smaller vertical distance from the upper surface of the substrate than the third value.

An integrated chip, comprising:

• a gate structure arranged over a semiconductor substrate, wherein the semiconductor substrate comprises interior surfaces forming source/drain recesses along opposing sides of the gate structure;
• source/drain regions arranged within the source/drain recesses;
• and
• wherein the source/drain regions comprise a strain inducing component having a strain inducing component concentration profile that changes from a first concentration at a first position, to a second concentration at a second position overlying the first position, to a third concentration at a third position overlying the second position and vertically below a bottommost surface of the gate structure, the first concentration being larger than the second concentration and smaller than the third concentration.