Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate provided with an active pattern;
• a channel pattern on the active pattern, the channel pattern comprising semiconductor patterns, which are vertically stacked to be spaced apart from each other;
• a source/drain pattern connected to the semiconductor patterns;
• a gate electrode on the semiconductor patterns, the gate electrode comprising a first portion interposed between a first semiconductor pattern and a second semiconductor pattern, which are two adjacent semiconductor patterns of the semiconductor patterns;
• and
• a gate insulating layer interposed between the first portion of the gate electrode and each of the first and second semiconductor patterns,
• wherein the first portion of the gate electrode has a sandglass shape,
• wherein the first portion comprises a lower portion, an upper portion, and an interface between the lower portion and the upper portion,
• wherein a width of the first portion decreases as a height is lowered from an upper surface of the first portion toward the interface, has a minimum value at the interface, and increases as the height is lowered from the interface toward a lower surface of the first portion,
• wherein a volume of the lower portion is larger than a volume of the upper portion,
• wherein the first semiconductor pattern comprises a first channel recess which is adjacent to the lower portion,
• wherein the second semiconductor pattern comprises a second channel recess which is adjacent to the upper portion, and
• wherein a first depth of the first channel recess is larger than a second depth of the second channel recess.

A semiconductor device, comprising:

• a substrate including an active region;
• a device isolation layer defining an active pattern on the active region;
• a channel pattern and a source/drain pattern on the active pattern, the channel pattern comprising semiconductor patterns, which are vertically stacked to be spaced apart from each other;
• a gate electrode on the semiconductor patterns, the gate electrode comprising portions respectively interposed between two adjacent semiconductor patterns among the semiconductor patterns;
• a gate insulating layer enclosing each portion of the portions of the gate electrode;
• a gate spacer on a side surface of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer insulating layer on the gate capping pattern;
• an active contact penetrating the interlayer insulating layer and electrically connected to the source/drain pattern;
• a metal-semiconductor compound layer interposed between the active contact and the source/drain pattern;
• a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer comprising a power line and a first interconnection line, which are electrically connected to the active contact and the gate contact, respectively;
• and
• a second metal layer on the first metal layer,
• wherein the second metal layer comprises a second interconnection line, which is electrically connected to the first metal layer,
• wherein the semiconductor patterns comprise channel recesses, respectively, and
• wherein depths of the channel recesses decrease as a distance increases in a vertical direction from a lowermost semiconductor pattern among the semiconductor patterns toward an uppermost semiconductor pattern among the semiconductor patterns.