Semiconductor device with backside interconnection and method for forming the same

A method of forming a memory circuit, comprising:

• forming a first active region and a second active region over a substrate;
• forming a gate structure over the substrate, wherein the gate structure has a first portion engaging the first active region in forming a first pull-down transistor of the memory circuit and a second portion engaging the second active region in forming a second pull-down transistor of the memory circuit;
• forming a gate-cut feature isolating the first and second portions of the gate structure;
• forming a first source/drain feature of the first pull-down transistor and a second source/drain feature of the second pull-down transistor, wherein the first and second source/drain features are disposed on two opposing sides of the gate-cut feature;
• selectively etching the first and second active regions from a backside of the substrate to form a trench, wherein the trench exposes bottom surfaces of the first and second source/drain features and the gate-cut feature;
• and
• depositing a conducive material in the trench to form a backside conductive feature landing on the bottom surfaces of the first and second source/drain features and the gate-cut feature.

A method, comprising:

• forming first and second active regions extending lengthwise along a first direction;
• forming a gate stack extending lengthwise along a second direction different from the first direction;
• forming a gate-cut feature dividing the gate stack into a first segment over the first active region and a second segment over the second active region, the gate-cut feature extending lengthwise along the first direction and disposed between the first and second active regions;
• epitaxially growing a first epitaxial feature on the first active region;
• epitaxially growing a second epitaxial feature on the second active region, the first and second epitaxial features disposed on two opposing sides of the gate-cut feature;
• forming a backside conductive feature electrically coupled to the first and second epitaxial features, the backside conductive feature including a first leg portion landing on a bottom surface of the first epitaxial feature, a second leg portion landing on a bottom surface of the second epitaxial feature, and a middle portion positioned under the gate-cut feature and physically connecting the first and second leg portions;
• and
• performing a planarization process to planarize a bottom surface of the backside conductive feature, wherein after the performing of the planarization process the middle portion of the backside conductive feature remains connecting the first and second leg portions.