Semiconductor package

A semiconductor package comprising:

• a structure;
• a semiconductor chip on an upper surface of the structure;
• a first adhesive layer between the upper surface of the structure and a lower surface of the semiconductor chip, the first adhesive layer in contact with the upper surface of the structure;
• a second adhesive layer between an upper surface of the first adhesive layer and the lower surface of the semiconductor chip, the second adhesive layer in contact with each of the upper surface of the first adhesive layer and the lower surface of the semiconductor chip, the second adhesive layer including a material different from the first adhesive layer;
• a recess in the first adhesive layer;
• a first conductive pad inside the recess, the first conductive pad in contact with the upper surface of the structure, an upper surface of the first conductive pad is at a lower vertical level than the upper surface of the first adhesive layer;
• a second conductive pad inside the second adhesive layer, the second conductive pad in contact with the lower surface of the semiconductor chip;
• and
• a bump connecting the first conductive pad and the second conductive pad, at least a part of the bump inside the recess, side walls of the bump being surrounded by each of the first adhesive layer and the second adhesive layer,
• wherein a width of the first adhesive layer in a horizontal direction is smaller than a width of the semiconductor chip in the horizontal direction.

A semiconductor package comprising:

• a structure;
• a semiconductor chip on an upper surface of the structure;
• a first conductive pad on the upper surface of the structure between the upper surface of the structure and the semiconductor chip;
• a second conductive pad on a lower surface of the semiconductor chip and vertically overlapping the first conductive pad;
• a bump connecting the first conductive pad and the second conductive pad;
• a first adhesive layer in contact with the upper surface of the structure, the first adhesive layer surrounding at least a portion of side walls of the bump and side walls of the first conductive pad;
• a second adhesive layer in contact with an upper surface of the first adhesive layer and the lower surface of the semiconductor chip, the second adhesive layer surrounding at least a portion of the side walls of the bump and side walls of the second conductive pads, the second adhesive layer including a material different from the first adhesive layer;
• and
• a molding layer on the upper surface of the structure and covering side walls of the first adhesive layer, side walls of the second adhesive layer, and side walls and an upper surface of the semiconductor chip,
• wherein a horizontal width of the semiconductor chip is smaller than a horizontal width of the second adhesive layer,
• wherein a horizontal width of the first adhesive layer is smaller than the horizontal width of the semiconductor chip,
• wherein an upper surface of the first conductive pad is at a lower vertical level than the upper surface of the first adhesive layer, and
• wherein at least a portion of the bump is in contact with the upper surface of the first adhesive layer.