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US 12,701,718 B2Granted
Semiconductor device
AssigneeSK hynix Inc.
InventorJae Hyun Han
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes: a bit line; a first barrier layer disposed on the bit line; a variable resistance layer disposed on the first barrier layer; a second barrier layer disposed on the variable resistance layer; and a word line disposed on the second barrier layer. A dielectric constant of the second barrier layer is greater than a dielectric constant of the first barrier layer.
Claims16
A semiconductor device comprising:
- a bit line;
- a first barrier layer disposed on the bit line;
- a variable resistance layer disposed on the first barrier layer;
- a second barrier layer disposed on the variable resistance layer;
- and
- a word line disposed on the second barrier layer, being in contact with the second barrier layer, and spaced apart from the variable resistance layer,
- wherein the second barrier layer is disposed between the variable resistance layer and the word line, and
- wherein a dielectric constant of the second barrier layer is greater than a dielectric constant of the first barrier layer.
5 more elements
A semiconductor device comprising:
- a bit line extending in a first direction;
- a word line extending in a second direction perpendicular to the first direction;
- and
- a memory cell having a pillar structure, which is disposed in a region in which the bit line and the word line overlap with each other,
- wherein the memory cell includes a first barrier layer adjacent to the bit line, a second barrier layer adjacent to the word line, and a variable resistance layer between the first barrier layer and the second barrier layer,
- wherein the second barrier layer is disposed between the variable resistance layer and the word line,
- wherein a dielectric constant of the second barrier layer is greater than a dielectric constant of the first barrier layer, and
- wherein a thickness of the second barrier layer is greater than a thickness of the first barrier layer.
5 more elements
A semiconductor device comprising:
- a first bit line extending in a first direction;
- a first memory cell overlapping with a portion of a top surface of the first bit line;
- a word line extending in a second direction perpendicular to the first direction on the first memory cell;
- a second memory cell overlapping with a portion of a top surface of the word line;
- and
- a second bit line extending in the first direction on the second memory cell,
- wherein the first memory cell includes a first barrier layer, a second barrier layer, and a first variable resistance layer disposed between the first and the second barrier layers,
- wherein the second memory cell includes a third barrier layer, a fourth barrier layer, and a second variable resistance layer disposed between the third and the fourth barrier layers,
- wherein the second barrier layer and the third barrier layer include ferroelectrics, and
- wherein the first variable resistance layer and the second variable resistance layer include a transition metal oxide.
7 more elements
Dependencies are inferred from the claim text.