Semiconductor memory device

A semiconductor memory device, comprising:

• a semiconductor substrate;
• a bit line and a source line that both extend in a second direction that is perpendicular to a first direction;
• and
• a plurality of memory cells on the semiconductor substrate,
• wherein each of the plurality of memory cells comprises:
• a first word line and a second word line that both extend in the first direction;
• an active region defined by a device isolation pattern in the semiconductor substrate;
• a spin-orbit torque (SOT) pattern having a first end electrically connected to the source line, and having a second end that is opposite to the first end;
• a magnetic tunnel junction pattern on the SOT pattern;
• a first transistor electrically connected to a first end of the magnetic tunnel junction pattern, wherein the first transistor is between the first end of the magnetic tunnel junction pattern and the bit line and configured to be controlled by the first word line;
• and
• a second transistor that contacts the second end of the SOT pattern, wherein the second transistor is between the second end of the SOT pattern and the bit line and is configured to be controlled by the second word line,
• wherein the first word line and the second word line cross the active region of a semiconductor substrate, and
• wherein an overlapping area between the first word line and the active region is smaller than an overlapping area between the second word line and the active region.

A semiconductor memory device, comprising:

• a semiconductor substrate comprising a first cell region and a second cell region, each of the first and second cell regions comprising first and second active patterns which protrude from the semiconductor substrate;
• a first writing word line on the first cell region, wherein the first writing word line crosses the first and second active patterns;
• a second writing word line on the second cell region, wherein the second writing word line crosses the first and second active patterns;
• a first reading word line on the first cell region, wherein the first reading word line is spaced apart from the first active pattern, crosses the second active pattern, and is between the first and second writing word lines;
• a second reading word line on the second cell region, wherein the second reading word line is spaced apart from the first active pattern, crosses the second active pattern, and is between the first reading word line and the second writing word line;
• first source/drain patterns at a side of the first writing word line and at a side of the second writing word line, respectively;
• second source/drain patterns between the first reading and writing word lines and between the second reading and writing word lines;
• a third source/drain pattern between the first and second reading word lines;
• first and second magnetic tunnel junction patterns electrically connected to the second source/drain patterns, respectively;
• first and second spin-orbit torque (SOT) patterns on the first and second magnetic tunnel junction patterns, respectively;
• a source line that crosses the first and second writing word lines and the first and second reading word lines and is electrically connected to the first and second SOT patterns;
• and
• a bit line that crosses the first and second writing word lines and the first and second reading word lines and is electrically connected to the second source/drain patterns,
• wherein, when measured from the semiconductor substrate, the bit line is at a first height, the source line is at a second height, and the first and second SOT patterns are at a third height, and
• wherein the third height is less than the first height and the second height.