Memory device and manufacturing method thereof

A method for manufacturing a memory device, comprising:

• forming a string of flash transistors on a substrate, comprising:
• forming gate stacks on the substrate, wherein each gate stack comprises a gate electrode and a charge trapping layer between the gate electrode and the substrate;
• and
• forming source/drain structures into the substrate at opposite sides of each gate stack, wherein heterojunctions are defined at interfaces between the substrate and the source/drain structures, and adjacent ones of the flash transistors share the source/drain structure in between;
• and
• forming a bit line over the substrate, wherein the bit line is routed to opposite ends of the string of flash transistors defined by two of the source/drain structures.

A method for manufacturing a memory device, comprising:

• forming a string of flash transistors on a substrate, comprising:
• defining channel structures at a surface of the substrate;
• forming gate stacks across the channel structures, wherein each gate stack comprises a gate electrode and a charge trapping layer between the gate electrode and an intersected one of the channel structures;
• and
• forming source/drain structures on the channel structures at opposite sides of each gate stack, wherein heterojunctions are defined at interfaces between the channel structures and the source/drain structures, and adjacent ones of the flash transistors share the source/drain structure in between;
• and
• forming a bit line over the substrate, wherein the bit line is routed to opposite ends of the string of flash transistors defined by two of the source/drain structures.