Dual-mode transmitter for low-power double-data rate (LPDDR)interface

A dual-mode transmitter configured to operate in either a non-return to zero (NRZ) mode or a pulse amplitude modulation (PAM)-4 mode, the dual-mode transmitter comprising:

• a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver;
• at least one serializer configured to serialize the transmission signal;
• a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal;
• a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver;
• a pre-driver configured to combine the differential signal obtained by the converting and the result code;
• a controller configured to control to generate a mode signal and a clock (CLK) signal for performing an operation in the PAM-4 mode or the NRZ mode according to a transmission rate of the transmission signal;
• and
• an output driver comprising at least one most significant bit (MSB) data path and at least one least significant bit (LSB) data path and configured to output the combined differential signal and result code as an output signal in a form of a combination of MSB data and LSB data,
• wherein the output driver further comprises a switch in each of the at least one MSB data path and the at least one LSB data path, the switch being controlled to be turned on or off according to the mode signal and the CLK signal such that the output driver is configured to be connected to the at least one MSB data path and the at least one LSB data path in the PAM-4 mode, and to the at least one MSB data path or the at least one LSB data path in the NRZ mode,
• wherein the at least one MSB data path comprises first and second MSB data paths each comprising an MSB data generator configured in a form of a driver of a pair of N-channel metal-oxide semiconductor (NMOS) transistors to generate the MSB data, a first additional driver controlled to be turned on or off according to a value obtained by a multiplication operation of the MSB data with an inverse signal of the mode signal, and a first switch controlled to be turned on or off according to a value obtained by a sum operation of the CLK signal and the mode signal, and
• wherein the at least one LSB data path comprises first and second LSB data paths each comprising an LSB data generator configured in a form of a driver of a pair of NMOS transistors to generate the LSB data, a second additional driver controlled to be turned on or off according to a value obtained by a multiplication operation of the LSB data with the inverse signal of the mode signal, and a second switch controlled to be turned on or off according to a value obtained by a sum operation of an inverse signal of the CLK signal and the mode signal or a value obtained by a multiplication operation of the inverse signal of the CLK signal and the inverse signal of the mode signal.