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US 12,700,863 B2Granted
Universal logic memory block using universal logic memory cells
AssigneeKorea University Research and Business Foundation
InventorsSang Sig Kim, Kyoung Ah Cho, Jong Seong Han, Jae Min Son, Ju Hee Jeon, Yun Woo Shin
Life of this patent
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Abstract
The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.
Claims14
A universal logic memory block, comprising:
- universal logic memory cells comprising a first network device and a second network device using a plurality of triple-gate silicon devices;
- a switch box that determines directions of an input voltage applied to the universal logic memory cells and an output voltage output from the universal logic memory cells;
- and
- a line switch that controls interconnection between the switch box and the universal logic memory cells,
- wherein, in a structure in which the universal logic memory cells are arranged according to preset settings, a combination logic operation function and memory function are performed according to interconnection control for a logic operation function of the universal logic memory cells according to the determined input voltage and output voltage directions.
2 more elements
Dependencies are inferred from the claim text.