Parasitic capacitance mitigation circuit for relaxation oscillators

A parasitic capacitance mitigation circuit for a relaxation oscillator comprising:

• a first switch coupled to a parasitic capacitance of a resistive sensing element;
• a second switch coupled between the parasitic capacitance and a reference voltage node, wherein the reference voltage node is configured to provide half of a supply voltage;
• and
• a pulse generator configured to:
• monitor a voltage at a node coupled to the parasitic capacitance;
• detect edges in a feedback signal from the relaxation oscillator, wherein the edges correspond to voltage transients at the node;
• and
• generate a pulse control signal in response to detecting the edges corresponding to the voltage transients, wherein in response to the pulse control signal, the first switch opens and the second switch closes to discharge the parasitic capacitance through the second switch to the reference voltage node.

A method of operating a parasitic capacitance mitigation circuit for a relaxation oscillator circuit, comprising:

• monitoring, by a pulse generator, a voltage at a node coupled to a parasitic capacitance of a resistive sensing element;
• detecting, by the pulse generator, a voltage transient at the node;
• generating, by the pulse generator, a pulse control signal in response to detecting the voltage transient;
• and
• opening a first switch and closing a second switch in response to the pulse control signal to discharge the parasitic capacitance through the second switch, wherein the first switch coupled to the parasitic capacitance of the resistive sensing element and the second switch is coupled between the parasitic capacitance and a reference voltage node.