Half-bridge switch arrangement

Half-bridge switch arrangement (1, 100) having a plurality of parallel-connected half-bridges (5), each half-bridge (5) having a first semiconductor switching element (11, 111) and a second semiconductor switching element (21, 121), the half-bridge switch arrangement comprising:

• a first busbar (30, 130), to which a first terminal of each of the first semiconductor switching elements (11, 111) is electrically connected,
• a second busbar (70, 170), to which a second terminal (115) of each of the first semiconductor switching elements (11, 111) and a first terminal of each of the second semiconductor switching elements (21, 121) are electrically connected,
• a third busbar (40, 140), to which a second terminal (125) of each of the second semiconductor switching elements (21, 121) is electrically connected, and
• a heat sink (180),
• wherein the first busbar (30, 130) has a first section (131) and a plurality of second sections (132), the second sections (132) of the first busbar (130) adjoining the first section (131) of the first busbar (130), so that a notch (135) is provided between each of the individual second sections of the first busbar (130),
• wherein one of the plurality of first semiconductor switching elements (11, 111) is arranged at each of the second sections (132) of the first busbar (130),
• wherein the second busbar (70, 170) has a first section (171) and a plurality of second sections (172), the second sections (172) of the second busbar (170) adjoining the first section (171) of the second busbar (170), so that a notch (175) is provided between each of the individual second sections (172) of the second busbar (170),
• wherein one of the plurality of second semiconductor switching elements (21, 121) is arranged at each of the second sections (172) of the second busbar (170),
• wherein the first busbar (130) and the second busbar (170) are arranged relative to each other such that the second sections (172) of the second busbar (170) are arranged within the notches (135) between the second sections (132) of the first busbar (130) in a projection onto the main plane of extension of the first busbar (130), and in that the second sections (132) of the first busbar (130) are each arranged within the notches (175) between the second sections (172) of the second busbar (170) in a projection onto the main plane of extension of the second busbar (170),
• wherein the third busbar (40, 140) is arranged on a first side of the arrangement comprising the first busbar (30, 130) and the second busbar (70, 170), which side comprises the first semiconductor switching elements (11, 111) and the second semiconductor switching elements (21, 121), and
• wherein the heat sink (180) is arranged on a second side of the arrangement comprising the first busbar (30, 130) and the second busbar (70, 170) opposite the first side.