Power conversion device with a configuration to prevent a malfunction caused by a soft error
AssigneeTMEIC Corporation
InventorHiroki Shigeta
Life of this patent
Estimating the term…
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AssigneeTMEIC Corporation
InventorHiroki Shigeta
Estimating the term…
A first controller includes a first processor and a first memory. A second controller includes a second processor and a second memory. In transmitting data from the first controller to the second controller, the first controller repeatedly performs a write operation of writing transmitted data into the first memory in accordance with a clock signal, and reads the transmitted data from the first memory and outputs the transmitted data. The second controller writes the received data into the second memory in accordance with the clock signal, and reads the received data from the second memory in accordance with the clock signal. When a plurality of data values of the received data read from the second memory match each other in a plurality of consecutive clock cycles including a current clock cycle, the second controller transmits the data value of the current clock cycle to the second processor.
A power conversion device comprising:
Dependencies are inferred from the claim text.