Fully scannable memory arrays
AssigneeSambaNova Systems, Inc.
InventorsThomas A. Ziaja, Paul J. Jordan
Life of this patent
Estimating the term…
Abstract
An array of memory cells can be configured into one or more scan chains that uses non-overlapping scan word line pulses in a direction opposite to a direction of the scan chain to shift scan bits in the direction of the scan chain from a scan chain input to a scan chain output. A memory cell may include a latch and a scan input multiplexer. The array includes a pulse generator to derive a pulse generator output from a clock pulse, and a digital delay line to generate the non-overlapping scan word line pulses from the pulse generator output. The scan chain may include a latch from an input buffer and may scan multiple columns or rows.
Claims13
An array of memory cells, comprising a scan chain that shifts scan bits in adjacent memory cells in the scan chain using non-overlapping scan word line pulses to clock successive memory cells in the scan chain, wherein a shift direction of the scan chain is along a column of memory cells.
A method of scanning an array of memory cells arranged in N rows and C columns, the array comprising a scan chain, the method comprising:
- shifting scan bits in adjacent memory cells in the scan chain using non-overlapping scan word line pulses to clock successive memory cells in the scan chain, wherein a shift direction of the scan chain is along a column of memory cells.
An array of memory cells arranged in N rows, numbered 0 through N−1, and C columns, numbered 0 through C−1, each row comprising a word line multiplexer, and each column comprising a first scan multiplexer, a second scan multiplexer, a read multiplexer, and a column buffer cell, wherein:
- each word line multiplexer, each first scan multiplexer, and each second scan multiplexer has a first input, a second input, and a scan enable input, and is configured to couple the first input with an output when the scan enable input is de-asserted and to couple the second input with the output when the scan enable input is asserted;
- the second input of the first scan multiplexer in column 0 is coupled with a scan chain input;
- in each column:
- the output of the first scan multiplexer is coupled with an input of the column buffer cell;
- an output of the column buffer cell is coupled with an input of the memory cell in row 0 and with the first input of the second scan multiplexer;
- the output of the second scan multiplexer is coupled with inputs of the memory cells in rows 1 through N−1;
- outputs of memory cells in rows 0 through N−1 are coupled with inputs of the read multiplexer;
- and
- an output of the read multiplexer is coupled with the second input of the second scan multiplexer;
- in each column c wherein c ranges from 0 through N−2, the output of the memory cell (N−1, c) is coupled with the second input of the first scan multiplexer in column c+1;
- the output of memory cell (N−1, C−1) is coupled with a scan chain output;
- and
- in each row:
- the output of the word line multiplexer is coupled with CLK inputs of memory cells in columns 0 through C−1.
A method of scanning an array of memory cells, wherein the array comprises a scan chain including at least two columns, coupled in series, and wherein each column comprises M of the memory cells, numbered 0 through M−1, each with a memory cell enable input, a first scan multiplexer, a second scan multiplexer, a read multiplexer, and a column buffer cell, and the array comprises M cell multiplexers, each with an output coupled with one of the M memory cell enable inputs of the M memory cells of the at least two columns, the method comprising:
- copying a scan chain input value to a second input of the first scan multiplexer in a first column;
- asserting clock inputs of the column buffer cells;
- for each column:
- copying an output value of the first scan multiplexer to an input of the column buffer cell;
- copying an output value of the column buffer cell to an input of memory cell 0 and to a first input of the second scan multiplexer;
- copying an output value of the read multiplexer to a second input of the second scan multiplexer;
- copying an output value of the second scan multiplexer to inputs of memory cells m, wherein m ranges from 1 to M−1;
- copying output values of memory cells m to inputs of the read multiplexer, wherein m ranges from 0 to M−1;
- and
- for the first column copying an output value of memory cell M−1 to a second input of the first scan multiplexer in a second column;
- for a last column, copying an output value of memory cell M−1 to a scan chain output value;
- using a scan enable signal to select second inputs of the first scan multiplexer, the second scan multiplexer, and m cell multiplexers, wherein m ranges from 0 to M−1;
- for each cell multiplexer m, wherein m ranges backward from M−1 to 0, applying a pulse to a second input of the cell multiplexer to enable memory cells m to copy a memory cell input value to a memory cell output;
- and
- de-asserting the clock of the column buffer cells to enable the column buffers cells to copy their input values to their output.
Dependencies are inferred from the claim text.