Memory device with control elements for unselected defective and unselected non-defective memory blocks

A memory device comprising:

• a memory cell array including a block including:
• a first transistor connected to a first select gate line,
• a second transistor connected to a second select gate line, and
• a plurality of memory cells connected in series between the first transistor and the second transistor and each connected to one corresponding word line of a plurality of word lines;
• and
• a row control circuit including:
• a first control circuit configured to control an electrical state of the first select gate line based on a first control signal for setting the block to be in a selected state or an unselected state, and
• a second control circuit configured to control an electrical state of the second select gate line based on the first control signal and information indicating whether the block is a non-defective block or a defective block;
• wherein the row control circuit is configured to receive a second control signal for controlling a state of a voltage of the second select gate line, and
• the row control circuit includes:
• a first P-type transistor including a first terminal connected to a first power terminal,
• a second terminal connected to a first node, and
• a first gate configured to receive the second control signal,
• a second P-type transistor including a third terminal connected to the first node, a fourth terminal connected to a second node for transferring a signal to the switch circuit, and a second gate configured to receive the first control signal,
• a first N-type transistor including a fifth terminal connected to the second node, a sixth terminal connected to a second power terminal, and a third gate configured to receive the first control signal,
• a third P-type transistor including a seventh terminal connected to the first power terminal, an eighth terminal connected to the first node, and a fourth gate configured to receive the information,
• a second N-type transistor including a ninth terminal connected to the second node, a tenth terminal, and a fifth gate configured to receive the information, and
• a third N-type transistor including an eleventh terminal connected to the tenth terminal, a twelfth terminal connected to the second power terminal, and a sixth gate configured to receive the second control signal.