Non-volatile memory device and erase method thereof

A non-volatile memory device comprising:

• a memory cell array including a plurality of cell strings extending on a substrate in a vertical direction, each of the plurality of cell strings comprising:
• a first end and a second end;
• a plurality of memory cells connected in series between a third end and a fourth end, and respectively connected to a plurality of word lines divided into a first word line group and a second word line group;
• a string selection transistor having a first end and a second end connected to the third end;
• a ground selection transistor having a first end and a second end connected to the fourth end;
• and
• an erase control transistor having a first end connected to at least one of the first ends of the string selection transistor and the ground selection transistor and a second end connected to at least one of the first end and the second end of each of the plurality of cell strings;
• and
• a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a first target level and to apply a second bias voltage higher than the first bias voltage to the second word line group in a second period after the first period, during an erase operation for the memory cell array.

An erase method of a non-volatile memory device including a plurality of cell strings stacked on a substrate in a vertical direction, each of the plurality of cell strings including a first end and a second end, and a string selection transistor, a plurality of memory cells, a ground selection transistor, and an erase control transistor connected in series between the first end and the second end, the erase method comprising:

• increasing a voltage applied to one end of the erase control transistor connected to at least one of the first end and the second end of each of the plurality of cell strings to a level of an erase voltage in a first period of an erase operation period;
• applying a first bias voltage to a plurality of word lines connected to the plurality of memory cells in the first period;
• and
• applying a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.