Memory device with improved driver operation and methods to operate the memory device
AssigneeMicron Technology, Inc.
InventorFerdinando Bedeschi
Life of this patent
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Abstract
The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive a first one of the access lines to a read/program voltage through the two-transistor driver, during a PULSE phase and drive a second one of the access lines physically adjacent to the first one of the access lines to a shielding voltage through the two-transistor driver, during the PULSE phase.
Claims20
A memory device comprising:
- memory cells at cross points of access lines of a memory array;
- and
- a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to:
- drive a first one of the access lines to a first read/program voltage comprising a positive voltage via a source line of the P-type transistor of the two-transistor driver, during a PULSE phase, when the first one of the access lines is an addressed access line and while a source line of the N-type transistor is at a floating voltage and a gate line of the P-type transistor and a gate line of the N-type transistor are at a discharging voltage;
- drive the first one of the access lines to a second read/program voltage comprising a negative voltage via the source line of the N-type transistor of the two-transistor driver, during the PULSE phase, when the first one of the access lines is the addressed access line and while the source line of the P-type transistor is at the floating voltage and the gate line of the P-type transistor and the gate line of the N-type transistor are at the discharging voltage;
- and
- drive the first one of the access lines physically adjacent to a second one of the access lines to a shielding voltage through the two-transistor driver, during the PULSE phase, when the first one of the access lines is an unaddressed access line and the second one of the access lines is the addressed access line.
A method to operate a memory device, the method comprising:
- during a PULSE phase;
- driving an access line coupled a memory cell to a first read/program voltage comprising a positive voltage through a P-type transistor of a two-transistor driver by:
- applying the first read/program voltage via a source line of the P-type transistor while a source line of an N-type transistor of the two-transistor driver is at a floating voltage, wherein the P-type transistor is connected to the N-type transistor;
- and
- applying a discharging voltage to a gate line of the P-type transistor and a gate line of the N-type transistor.
A system comprising a memory array and a controller configured to:
- drive a first access line to a read/program voltage through a first two-transistor driver by applying a positive read/program voltage to a source line of a P-type transistor of the first two-transistor driver or a negative read/program voltage to a source line of an N-type transistor of the first two-transistor driver, and applying a discharging voltage to a gate line of the P-type transistor and a gate line of the N-type transistor, during a PULSE phase;
- and
- drive a second access line physically adjacent to the first access line to a shielding voltage through a second two-transistor driver, during the PULSE phase.
Dependencies are inferred from the claim text.