In-memory computation device for implementing at least a multilayer neural network

An in-memory computation (IMC) device configured to receive an input signal comprising a plurality of input data and to provide at least a plurality of intermediate output data indicative of a respective final output signal which is a function of the input signal, the IMC device, comprising:

• a word line activation circuit configured to receive the input signal and to provide a plurality of word line activation signals, each being a function of a respective input datum of the plurality of input data;
• a biasing circuit configured to provide a biasing voltage;
• a memory array comprising a plurality of memory cells having a matrix arrangement with a number M of columns and a number N′ of rows and each coupled to a respective bit line and to a respective word line in such a way that each of the M bit lines is electrically coupled to N′ respective memory cells and each of the N′ word lines is electrically coupled to M respective memory cells, the bit lines being configured to each receive the biasing voltage, the memory cells being configured to each store a respective computational weight and to each receive a respective word line activation signal of the word line activation signals from the respective word line, the memory cells being configured to be traversed each by a respective cell current which is a function of the biasing voltage, the respective word line activation signal and the respective computational weight, each bit line being configured to be traversed by a respective bit line current which is a sum of the cell currents of the memory cells connected to the bit line;
• a plurality K of selectors each coupled to a respective part of the bit lines and each configured to select either one or none of the respective bit lines;
• a digital detector for each selector, each digital detector coupled for electrical connection through the respective selector with the respective bit line selected by the respective selector, the digital detectors being configured to sample the respective bit line currents traversing the respective bit lines to which the digital detectors are electrically coupled and, in response to the sampled bit line currents, provide the respective intermediate output data;
• a first multiply and accumulate (MAC) circuit defined by a first part of the selectors, the respective digital detectors, the bit lines coupled to the first part of the selectors and the memory cells along the bit lines coupled to the first part of the selectors, the first MAC circuit being configured to perform multiply and accumulate (MAC) operations relating to a first neural network defined by the computational weights of the memory cells along the bit lines coupled to the first part of the selectors and comprising a number R1 of layers;
• and
• at least a second multiply and accumulate (MAC) circuit defined by a second part of the selectors, the respective digital detectors, the bit lines coupled to the second part of the selectors and the memory cells along the bit lines coupled to the second part of the selectors, the at least one second MAC circuit being configured to perform multiply and accumulate (MAC) operations relating to at least one second neural network defined by the computational weights of the memory cells along the bit lines coupled to the second part of the selectors and comprising a number R2 of layers;
• wherein each selector, the respective digital detector, the respective bit lines coupled to the selector and the part of memory cells arranged along the bit lines coupled to the selector form a respective multiply and accumulate (MAC) assembly of the first MAC circuit or of the at least one second MAC circuit;
• wherein each MAC assembly of the first MAC circuit has a respective number R1 of said bit lines coupled to the respective selector, the number R1 of the bit lines coupled to the respective selector being equal to the number R1 of layers of the first neural network in such a way that the computational weights of the memory cells of the respective r1-th bit lines of the MAC assemblies of the first MAC circuit together define the respective r1-th layer of the first neural network, with r1=1, . . . , R1 for each MAC assembly of the first MAC circuit;
• wherein each MAC assembly of the at least one second MAC circuit has a respective number R2 of said bit lines coupled to the respective selector, the number R2 of the bit lines coupled to the respective selector being equal to the number R2 of layers of the second neural network in such a way that the computational weights of the memory cells of the respective r2-th bit lines of the MAC assemblies of the at least one second MAC circuit together define the respective r2-th layer of the second neural network, with r2=1, . . . , R2 for each MAC assembly of the at least one second MAC circuit;
• wherein a number K of MAC assemblies is equal to, or greater than, the greater of a maximum number of final output data of the final output signal generated by the first MAC circuit and a maximum number of final output data of the final output signal generated by the at least one second MAC circuit;
• wherein, for each layer of the first neural network, each MAC assembly of the first MAC circuit is configured to generate a respective intermediate output datum of the intermediate output data, the final output data of the final output signal generated by the first MAC circuit as a function of said layer of the first neural network being dependent on the respective intermediate output data generated by the MAC assemblies of the first MAC circuit as a function of said layer of the first neural network;
• and
• wherein, for each layer of the at least one second neural network, each MAC assembly of the at least one second MAC circuit is configured to generate a respective intermediate output datum of the intermediate output data, the final output data of the final output signal generated by the at least one second MAC circuit as a function of said layer of the at least one second neural network being dependent on the respective intermediate output data generated by the MAC assemblies of the at least one second MAC circuit as a function of said layer of the at least one second neural network.