US 12,699,833 B2 · Systems and methods for obfuscating a circuit design

Abstract

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

Claims19

Dependent claims

A method comprising:

accessing a plurality of parameters for designing an integrated circuit from a specification stored in a specification database;
generating a circuit design of the integrated circuit, wherein the circuit design is generated based on the plurality of parameters, wherein the circuit design is generated when access to a circuit design tool is provided via a computer network and a user account;
generating a software tool to control access by another user account to one or more portions of the circuit design;
generating a layout design based on a plurality of components of the circuit design;
generating an obfuscator tool that obfuscates each component, from the plurality of components, by transforming layout features associated with the circuit design into a generic layout feature representation that excludes scaled representations of the layout features to generate an obfuscated design;
testing the circuit design and the layout design based on the plurality of parameters to generate a plurality of test results;
and
providing a report including the plurality of test results.

5 more elements

A computer system comprising:

a processor configured to:
access a plurality of parameters for designing an integrated circuit from a specification stored in a specification database;
generate a circuit design of the integrated circuit, wherein the circuit design is generated based on the plurality of parameters, wherein the circuit design is generated when access to a circuit design tool is provided via a computer network and a user account;
generate a software tool to control access by another user account to one or more portions of the circuit design;
generate a layout design based on a plurality of components of the circuit design;
generate an obfuscator tool that is configured to overlay the layout design with an opaque portion that hides one or more proprietary layout features while enabling routing between input ports and output ports;
test the circuit design and the layout design based on the plurality of parameters to generate a plurality of test results;
and
provide a report including the plurality of test results;
and
a memory device coupled to the processor.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/745,814Filed 16 May 2022 · continuation

Priority

8 Jul 2016

Published

US 2022/0027544 A11 Sep 2022

Granted

4 Aug 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3308
Design verification, e.g. functional simulation or model checking: using simulation

Family

Application62/359,858Us provisional application · filed 8 Jul 2016

Application15/633,412Parent of this continuation · filed 26 Jun 2017

Application16/564,536Parent of this continuation · filed 9 Sep 2019

US 10,423,748 B2Parent of this continuation · filed 24 Sep 2019

Application16/879,045Parent of this continuation · filed 20 May 2020

US 10,671,700 B2Parent of this continuation · filed 2 Jun 2020

Application17/493,576Parent of this continuation · filed 4 Oct 2021

US 11,301,609 B2Parent of this continuation · filed 12 Apr 2022

US 2022/0277126 A1Pre-grant publication · published 1 Sep 2022

US 11,775,722 B2Parent of this continuation

US 2018/0011959 A1Published application

US 2019/0392105 A1Published application

US 2020/0285795 A1Published application

US 2022/0027544 A1Published application

US 12,699,833 B2This patent

From the US filing history. Foreign family members aren’t listed.

Systems and methods for obfuscating a circuit design

Life of this patent

Systems and methods for obfuscating a circuit design

Life of this patent

Abstract

Claims19