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US 12,699,832 B2Granted
Multi-path routing in a network on chip
AssigneeXilinx, Inc.
InventorsSurya Rajendra Swamy Saranam Chongala, Nikhil Arun Dhume, Krishnan Srinivasan, Dinesh D. Gaitonde
Life of this patent
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Abstract
Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.
Claims20
An integrated circuit, comprising:
- a first circuit element;
- a second circuit element;
- and
- a network on a chip (NoC) configured to communicatively couple the first and second circuit elements, the NoC configured to:
- receive, at an ingress logic block, a packet from the first circuit element to be transmitted to the second circuit element,
- determine that a destination of the packet uses multi-path routing (MPR) in the NoC, and
- assign an alias destination ID corresponding to the destination based on a desired bandwidth usage ratio of a plurality of paths used to transmit data from the ingress logic block to an egress logic block in the NoC, wherein each of the plurality of paths between the ingress logic block and the egress logic block has a different alias destination ID.
4 more elements
A method, comprising:
- receiving, at an ingress logic block of a NoC, a packet from a first circuit element to be transmitted to a second circuit element coupled to the NoC;
- determining that a destination of the packet uses multi-path routing (MPR) in the NoC;
- and
- assigning an alias destination ID corresponding to the destination based on a desired bandwidth usage ratio of a plurality of paths used to transmit data from the ingress logic block to an egress logic block in the NoC, wherein each of the plurality of paths between the ingress logic block and the egress logic block has a different alias destination ID.
1 more element
An integrated circuit, comprising:
- a first circuit element assigned a first ID;
- a second circuit element assigned a second ID different from the first ID;
- and
- a NoC comprising:
- an ingress logic block configured to receive packets from the first and second circuit elements to transmit through the NoC to a same egress logic block in the NoC;
- wherein the ingress logic block is configured to:
- assign a first alias destination ID corresponding to a first path through the NoC used by packets received from the first circuit element to reach the egress logic block, and
- assign a second alias destination ID corresponding to a second path through the NoC used by packets received from the second circuit element to reach the egress logic block.
5 more elements
Dependencies are inferred from the claim text.