Continuous impairment of a chip upon detecting a damaged package

A non-transitory computer-readable medium comprising an isolated Root of Trust (ROT) code storing instructions that, when executed by a processor, cause the processor to:

• determine whether an attack is being attempted on an Integrated Circuit (IC) during at least a powering on of the IC;
• decrypt an identity package that resides at a non-volatile memory of the IC using a secret accessed by the processor, wherein the identity package is configured in a decrypted state by use of the secret at the non-volatile memory;
• discover, based on monitoring data from at least one sensor operably coupled to the processor, that the attack is being attempted on a package of the IC;
• determine whether a debug package is present;
• and
• in response to a determination that the debug package is not present, execute a tamper resistance process as an active response to the attack to prevent using of the secret and the identity package from being in the decrypted state in the non-volatile memory of the IC,
• wherein the tamper resistance process includes:
• causing the identity package to transition from the decrypted state to an encrypted state by encrypting the identity package;
• and
• at least one of overwriting, changing, or reordering one or more bits of the secret to generate a modified secret that is unable to decrypt the identity package resulting in an inability to verify that the IC is compliant for operating.

A computing device comprising:

• a processor;
• and
• a non-transitory computer-readable media storing instructions comprising Root-Of-Trust (ROT) code that, when executed by the processor, causes the processor to perform features comprising:
• decrypting an identity package that resides at a non-volatile memory of an Integrated Circuit (IC) using a secret accessible by the processor, wherein the identity package includes identification data usable by the ROT code to determine that the IC is compliant for operating;
• discovering, based on monitoring data from at least one sensor operably coupled to the processor, that an attack is at least being attempted on a package of the IC;
• determining using a secure channel whether a debug package is present in response to the attack;
• and
• in response to a determination that the debug package is not present, executing a tamper resistance process as an active response to the attack to prevent using of the secret and the identity package from being placed or remaining in a decrypted state in the non-volatile memory of the IC,
• wherein the tamper resistance process includes:
• causing the identity package to transition from the decrypted state to an encrypted state by encrypting the identity package;
• and
• at least one of overwriting, changing, or reordering one or more bits of the secret to generate a modified secret that is unable to decrypt the identity package resulting in an inability to verify that the IC is compliant for operating.