Apparatuses and methods for configurable ECC modes
AssigneeMicron Technology, Inc.
InventorsSujeet Ayyapureddi, Scott E. Smith
Life of this patent
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Abstract
Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.
Claims16
A method comprising:
- writing a value to a mode register of a memory device to set the memory device in a first mode or a second mode;
- writing data to a memory array of the memory device;
- accessing a first percentage of the memory array in the first mode or a second percentage of the memory array in the second mode;
- and
- writing a same number of bits of data to the memory array when accessing the first percentage of the memory array in the first mode or when accessing the second percentage of the memory array in the second mode.
A method comprising:
- writing a value to a mode register of a memory device to set an error correction code (BCC) mode of the memory device to one of a first mode or a second mode;
- accessing a first percentage of addresses of the memory array of the memory device to store data when the ECC is in the first mode;
- accessing a second percentage of addresses of the memory array of the memory device to store data when the ECC is in the second mode, wherein the first percentage is greater than the second percentage;
- and
- accessing the memory array one time to write the data in both the first mode and the second mode.
A method comprising:
- writing a value to a mode register of a memory device to set the memory device in a first mode or a second mode;
- reading data from a memory array of the memory device;
- receiving a signal from the memory device that indicates single bit error correction in the data when the memory device is in the first mode and double bit error detection in the data when the memory device is in the second mode;
- addressing a first percentage of the memory array in the first mode;
- and
- addressing a second percentage of the memory array in the second mode.
A system comprising:
- a memory device comprising:
- a mode register configured to store a value, wherein based on the value the memory device operates in a first mode or a second mode;
- a memory bank comprising a first plurality of column planes, a second plurality of column planes, and an extra column plane;
- and
- a column decoder configured to store data in a selected one of the first or the second plurality of column planes and parity bits in the extra column plane as part of an access operation in the first mode and configured to store the data in a selected one of the first or the second plurality of column planes, store the parity bits in at least one of non-selected ones of the first or the second plurality of column planes or in the extra column plane as part of the second mode;
- and
- a controller configured to write the value to the mode register to set the memory in the first mode or the second mode, wherein the controller is configured to write data to the memory device with a different amount of latency in the first mode as compared with the second mode.
Dependencies are inferred from the claim text.