US 12,699,565 B2Granted

Processor employing instruction that performs a bitwise majority vote operation

AssigneeApogee Semiconductor, Inc.

InventorDavid A. Grant

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Abstract

A system includes a feedback control loop signal path. Circuitry of the signal path includes three processors. Each processor (“slice”) includes an ADC, a digital signal processor (DSP), and a DAC. The DSPs of the three slices execute identical programs of instructions, and are clocked in unison so that at any given time they are executing the same instruction. The DSP of the slice executes an instruction that performs a “register bitwise majority vote” (RMAJ) operation. The instruction identifies a register of the slice, and the data content of this register is output via a bus to the two other slices. The DSP performs a bitwise majority vote on: 1) the data content of the register, 2) the data content of the corresponding register in each of the other two slices. The result of the bitwise majority vote is written into the register of the slice.

Claims24

Dependent claims

A method, comprising:

(a) storing a first instruction in a first processor;
(b) storing a first register value in a first register of the first processor;
(c) storing a second instruction in a second processor;
(d) storing a second register value in a second register of the second processor;
(e) storing a third instruction in a third processor;
(f) storing a third register value in a third register of the third processor;
(g) executing the first instruction on the first processor, wherein the executing of (g) causes the first register value to be output from the first processor and to be supplied to the second processor and to the third processor;
(h) executing the third instruction on the third processor, wherein the executing of (h) causes the third register value to be output from the third processor and to be supplied to the first processor and to the second processor;
and
(i) executing the second instruction on the second processor, wherein the executing of (i) causes the second register value to be output from the second processor and to be supplied to the first processor and to the third processor, wherein the executing of (i) further causes the second processor to perform a bitwise majority vote operation on the first register value, the second register value and the third register value thereby generating a result value, and wherein the executing of (i) further causes the result value to be written into the second register of the second processor.

7 more elements

An integrated circuit, comprising:

a first digital processor circuit comprising:
a first input port;
a second input port;
a register that stores a register value;
a memory that stores an instruction, wherein the instruction includes a register identifying value that identifies the register;
and
means for (a) reading the instruction from the memory, (b) executing the instruction by performing a bitwise majority vote operation on the register value, a first value received onto the first digital processor circuit via the first input port, and a second value received onto the first digital processor circuit via the second input port, thereby generating a result value, and writing the result value into the register, wherein the writing of the result value into the register by the means is a conditional write that only occurs if a condition is satisfied, and wherein the means is also for determining whether the condition is satisfied, wherein the condition is satisfied if a first address value and a second address value are both bitwise equal to the register identifying value, wherein the first address value is a value received onto the first digital processor circuit via a third input port, and wherein the second address value is a value received onto the first digital processor circuit via a fourth input port.

4 more elements

An integrated circuit, comprising:

a first digital processor circuit comprising:
means for executing an instruction such that a bitwise majority vote operation is performed on a register value stored in a selectable register of the first digital processor circuit and two other register values thereby obtaining a result value, and for writing the result value into the selectable register of the first digital processor circuit;
a second digital processor circuit comprising:
means for executing an instruction such that a bitwise majority vote operation is performed on a register value stored in a selectable register of the second digital processor circuit and two other register values thereby obtaining a result value, and for writing the result value into the selectable register of the second digital processor circuit;
a third digital processor circuit comprising:
means for executing an instruction such that a bitwise majority vote operation is performed on a register value stored in a selectable register of the third digital processor circuit and two other register values thereby obtaining a result value, and for writing the result value into the selectable register of the third digital processor circuit;
and
a digital majority voter circuit having a first input, a second input, and a third input, wherein the first input is coupled to receive a digital value output by the first digital processor circuit, wherein the second input is coupled to receive a digital value output by the second digital processor circuit, and wherein the third input is coupled to receive a digital value output by the third digital processor circuit,
wherein the means for executing of the first digital processor circuit receives one of the two other register values from the second processor circuit and receives the other of the two other register values from the third processor circuit, wherein the means for executing of the second digital processor circuit receives one of the two other register values from the first processor circuit and receives the other of the two other register values from the third processor circuit, and wherein the means for executing of the third digital processor circuit receives one of the two other register values from the first processor circuit and receives the other of the two other register values from the second processor circuit.

6 more elements

An integrated circuit, comprising:

a first digital processor circuit comprising:
a processor output register;
and
means for executing an instruction such that a bitwise majority vote operation is performed on a register value stored in a selectable register of the first digital processor circuit and two other register values thereby obtaining a result value, and for writing the result value into the selectable register of the first digital processor circuit;
a second digital processor circuit comprising:
a processor output register;
and
means for executing an instruction such that a bitwise majority vote operation is performed on a register value stored in a selectable register of the second digital processor circuit and two other register values thereby obtaining a result value, and for writing the result value into the selectable register of the second digital processor circuit;
a third digital processor circuit comprising:
a processor output register;
and
means for executing an instruction such that a bitwise majority vote operation is performed on a register value stored in a selectable register of the third digital processor circuit and two other register values thereby obtaining a result value, and for writing the result value into the selectable register of the third digital processor circuit;
and
a digital majority voter circuit having a first input, a second input, and a third input, wherein the first input is coupled to receive a register value stored in the processor output register of the first digital processor circuit, wherein the second input is coupled to receive a register value stored in the processor output register of the second digital processor circuit, and wherein the third input is coupled to receive a register value stored in the processor output register of the third digital processor circuit,
wherein the means for executing of the first digital processor circuit receives one of the two other register values from the second processor circuit and receives the other of the two other register values from the third processor circuit, wherein the means for executing of the second digital processor circuit receives one of the two other register values from the first processor circuit and receives the other of the two other register values from the third processor circuit, and wherein the means for executing of the third digital processor circuit receives one of the two other register values from the first processor circuit and receives the other of the two other register values from the second processor circuit.

12 more elements

Dependencies are inferred from the claim text.