Flexible test instruction set architecture

A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing a testing environment, wherein the testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM, wherein a device under test (DUT) is accessible by the command interface, and wherein the testing environment includes a test instruction set architecture (TISA), wherein the TISA includes a plurality of opcodes, wherein the plurality of opcodes configure the testing environment;
• programming a test sequence, by a user, wherein the test sequence includes one or more instructions from within the TISA;
• storing, in the instruction RAM, the test sequence that was programmed;
• fetching, by the FAD, a first instruction from the test sequence that was stored in the instruction RAM, wherein the fetching includes decoding the first instruction;
• translating, by the code exerciser, the first instruction, wherein the translating produces a first packetized communication, wherein the DUT is responsive to the first packetized communication;
• sending the first packetized communication, by the command interface, to the DUT;
• receiving a first packetized response, by the command interface, from the DUT, wherein the first packetized response is stored in a trace RAM;
• and
• reporting, to the user, the first packetized response that was stored in the trace RAM.

A computer system for instruction execution comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a testing environment, wherein the testing environment includes an instruction RAM, an instruction fetch and decode unit (FAD), a code exerciser, a command interface, and a trace RAM, wherein a device under test (DUT) is accessible by the command interface, and wherein the testing environment includes a test instruction set architecture (TISA), wherein the TISA includes a plurality of opcodes, wherein the plurality of opcodes configure the testing environment;
• program a test sequence, by a user, wherein the test sequence includes one or more instructions from within the TISA;
• store, in the instruction RAM, the test sequence that was programmed;
• fetch, by the FAD, a first instruction from the test sequence that was stored in the instruction RAM, wherein the fetching includes decoding the first instruction;
• translate, by the code exerciser, the first instruction, wherein the translating produces a first packetized communication, wherein the DUT is responsive to the first packetized communication;
• send the first packetized communication, by the command interface, to the DUT;
• receive a first packetized response, by the command interface, from the DUT, wherein the first packetized response is stored in a trace RAM;
• and
• report, to the user, the first packetized response that was stored in the trace RAM.