Semiconductor test key structure and test method of semiconductor structure
AssigneeUnited Semiconductor (Xiamen) Co., Ltd.
InventorsYa Xuan Zhuang, Wei-Chun Chang, You-Di Jhang, Chin-Chun Huang, Wen Yi Tan
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Abstract
The invention provides a semiconductor test key structure, which comprises a substrate, a plurality of gate structures located on the substrate, a plurality of thin film resistor layers, wherein each thin film resistor layer is located above one of the gate structures, and the thin film resistor layers are located in a dielectric layer, a test key circuit layer is located on the dielectric layer, wherein the test key circuit layer is a square wave pattern from a top view, and two contact pads are respectively connected with the test key circuit layer.
Claims16
A semiconductor test key structure, characterized in that:
- a substrate;
- a plurality of gate structures located on the substrate;
- a plurality of thin film resistor layers, wherein each thin film resistor layer is vertically overlapping with one of the gate structures, and the thin film resistor layers are located in a dielectric layer;
- a test key circuit layer located on the dielectric layer, wherein the test key circuit layer is a square wave pattern when viewed from a top view, wherein the square wave pattern comprises a plurality of strip patterns and a plurality of connection patterns, wherein each strip pattern is arranged along a first direction and each connection pattern is arranged along a second direction, and each connection pattern is connected in series with a respective head end of two adjacent strip patterns or a respective tail end of two adjacent strip patterns, so that the plurality of strip patterns and the plurality of connection patterns form a continuous square wave pattern;
- and
- two contact pads, which are respectively connected with two ends of the test key circuit layer.
A method for testing a semiconductor structure, characterized in that:
- providing a substrate;
- forming a plurality of gate structures on the substrate;
- forming a plurality of thin film resistor layers, wherein each thin film resistor layer is vertically overlapping with one of the gate structures, and the thin film resistor layers are positioned in a dielectric layer;
- forming a test key circuit layer on the dielectric layer, wherein the test key circuit layer is a square wave pattern when viewed from a top view, wherein the square wave pattern comprises a plurality of strip patterns and a plurality of connection patterns, wherein each strip pattern is arranged along a first direction and each connection pattern is arranged along a second direction, and each connection pattern is connected in series with a respective head end of two adjacent strip patterns or a respective tail end of two adjacent strip patterns, so that the plurality of strip patterns and the plurality of connection patterns form a continuous square wave pattern;
- forming two contact pads which are respectively connected with two ends of the test key circuit layer;
- applying a voltage to the two contact pads and gradually increasing the voltage;
- and
- observing whether any one of the plurality of thin film resistor layers exhibits an increase in resistance representing an open circuit condition.
Dependencies are inferred from the claim text.