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US 12,696,803 B2Granted
Die package including a semiconductor die having a cavity within which a passive component is positioned, IC package and manufacturing process thereof
AssigneesnD-HI Technologies Lab, Inc., Etron Technology, Inc.
InventorsHo-Ming Tong, Chao-Chun Lu
Life of this patent
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Abstract
A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.
Claims14
A die package, comprising:
- a semiconductor die with a first bonding pad and a conductive via in the semiconductor die;
- a passive component with a second bonding pad;
- a molding compound enclosing the semiconductor die;
- and
- a RDL layer over the semiconductor die, the RDL layer electrically connecting to the first bonding pad;
- wherein the semiconductor die has a cavity, the passive component is disposed inside the cavity of the semiconductor die, and the second bonding pad of the passive component is electrically connected with the conductive via in the semiconductor die.
3 more elements
Dependencies are inferred from the claim text.