Semiconductor structure and method for forming the same

A method for forming a semiconductor structure comprising:

• forming a plurality of FET devices over a semiconductor substrate, wherein each of the FET devices comprises a sacrificial gate structure and a source/drain;
• forming an etch stop layer over the substrate and the FET devices, wherein the etch stop layer covers top surfaces of the sacrificial gate structures and top surfaces of the sources/drains;
• forming an ILD structure over the etch stop layer, the substrate and the FET devices;
• forming a doped region in the ILD structure between the sacrificial gate structures of adjacent two FET devices, wherein a bottom and a sidewall of the doped region are in contact with the ILD structure, and the doped region is separated from the sources/drains of the FET devices by the ILD structure and the etch stop layer;
• removing portions of the ILD structure and portions of the etch stop layer;
• exposing the top surfaces of the sacrificial gate structures, wherein a top surface of the etch stop layer, a top surface of the ILD structure, a top surface of the doped region and the top surfaces of the sacrificial gate structures are aligned with each other;
• and
• replacing the sacrificial gate structures with metal gate structures;
• wherein the removing of the portions of the ILD structure and the portions of the etch stop layer comprises a CMP operation, and
• a removing rate of the doped region is lower than a removing rate of the ILD structure in the CMP operation.

A method for forming a semiconductor structure comprising:

• forming a FET device over a semiconductor substrate, wherein the FET device comprises a sacrificial gate structure and a source/drain;
• forming an etch stop layer over a top surface of the sacrificial gate structure and a top surface of the source/drain;
• forming an ILD structure over the etch stop layer, the substrate and the FET device;
• forming a patterned mask over the ILD structure, wherein the patterned mask overlaps the sacrificial gate structure;
• performing an ion implantation to form an nitrogen (N)-doped region in the ILD structure after the forming of the patterned mask, wherein the N-doped region is offset from the sacrificial gate structure and the N-doped region is separated from the source/drain of the FET device by the ILD structure;
• removing a portion of the ILD structure, a portion of the etch stop layer and a portion of the N-doped region;
• exposing the top surface of the sacrificial gate structure, wherein a top surface of the etch stop layer, a top surface of the ILD structure, a top surface of the N-doped region and the top surface of the sacrificial gate structure are aligned with each other;
• removing the sacrificial gate structure to form a gate trench;
• and
• forming a metal gate structure in the gate trench;
• wherein a concentration of the nitrogen in the N-doped region is between approximately 1.0E14 atom/cm3 and approximately 1.0E16 atom/cm3;
• further comprises a spacer disposed between the metal gate structure and the ILD structure, wherein sidewalls of the N-doped region are separated from the spacer by the ILD structure;
• wherein the N-doped region is separated from the CESL by the ILD structure wherein the N-doped region comprises a dielectric material same as that of the ILD structure.