Semiconductor device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTzuan-Horng Liu, An-Jhih Su, Mill-Jer Wang
Life of this patent
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Abstract
An embodiment is a method including a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein. The method also includes forming a second dielectric layer over the first dielectric layer and the first metallization pattern. The method also includes forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern. The method also includes performing a circuit probe test on the sacrificial pad. The method also includes after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad.
Claims20
A method comprising:
- forming a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein;
- forming a second dielectric layer over the first dielectric layer and the first metallization pattern;
- forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern;
- performing a circuit probe test on the sacrificial pad;
- after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad;
- and
- after removing the sacrificial pad, forming a first bond via in a third dielectric layer over the second dielectric layer and the first conductive feature, the first bond via being electrically coupled to the first conductive feature in the first metallization pattern, the third dielectric layer physically contacting the first conductive feature.
A method comprising:
- forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, the metallization patterns including a top metal layer including top metal structures;
- forming a passivation layer over the top metal structures of the first interconnect structure;
- forming a first opening through the passivation layer, a first top metal structure of the top metal structures being exposed through the first opening;
- forming a probe pad in the first opening and over the passivation layer, the probe pad being electrically connected to the first top metal structure;
- performing a circuit probe test on the probe pad, the probe pad being over and extending along a top surface of the passivation layer during the circuit probe test;
- after performing the circuit probe test, removing the probe pad;
- and
- after removing the probe pad, forming a bond pad and a bond via in dielectric layers over the passivation layer, the bond pad and bond via being electrically coupled to the first top metal structure of the top metal structures.
A structure comprising:
- a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein;
- a through substrate via extending through the first interconnect structure and the first substrate;
- a first top metal structure and a second top metal structure in a first dielectric layer over the first interconnect structure;
- a second dielectric layer over the second top metal structure and partially over the first top metal structure;
- a third dielectric layer over the second dielectric layer, the third dielectric layer extending through the second dielectric layer to physically contact the first top metal structure;
- a first bond via in the second and third dielectric layers over the first top metal structure, the first bond via being electrically coupled to the first top metal structure;
- a first bond pad in a fourth dielectric layer over the first bond via, the first bond pad being electrically coupled to the first bond via;
- a second bond via in the second and third dielectric layers over the second top metal structure, the second bond via being electrically coupled to the second top metal structure;
- and
- a second bond pad in a fourth dielectric layer over the second bond via, the second bond pad being electrically coupled to the second bond via.
Dependencies are inferred from the claim text.