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US 12,696,732 B2Granted
Semiconductor device, method of testing the same, and method of designing the same
AssigneeRenesas Electronics Corporation
InventorHiroko Yoshinaga
Life of this patent
Estimating the term…
Abstract
Signal delay, etc. in a signal path from an electrode pad to a functional block is reduced. An input-output block A and an input-output block B are connected to electrode pads. A functional block A is connected to the electrode pads via the input-output block A. A functional block B is connected to the electrode pads via the input-output block B. The functional block A and the functional block B are arranged at positions opposed to each other so as to sandwich the input-output block A and the input-output block B.
Claims10
A semiconductor device comprising:
- a plurality of electrode pads;
- a first input-output block coupled to each of the plurality of electrode pads;
- a second input-output block coupled to each of the plurality of electrode pads;
- a third input-output block coupled to each of the plurality of electrode pads;
- a first functional block coupled to each of the plurality of electrode pads via the first input-output block;
- a second functional block coupled to each of the plurality of electrode pads via the second input-output block;
- and
- a third functional block coupled to the each of the plurality of electrode pads via the third input-output block,
- wherein a first electrode pad of the plurality of electrode pads is located on the first input-output block and a second electrode pad of the plurality of electrode pads is located on the second input-output block,
- wherein each of the plurality of electrode pads is shared among the first, second, and third functional blocks via the first, second, and third input-output blocks, and
- wherein the first and second input-output blocks are located between the first functional block and the second functional block.
8 more elements
Dependencies are inferred from the claim text.