Manufacturing method of a SiC wafer with residual stress control

A method, comprising:

• forming a seed silicon carbide (SiC) layer on a substrate in a reaction chamber, the seed SiC layer having a thickness less than 10 nm, the substrate having a first end suspended by a first support and a second end suspended by a second support, the first end being opposite the second end along a first direction, the first and second supports each having a first portion with a first thickness along a second direction transverse to the first direction and a second portion with a second thickness along the second direction greater than the first thickness, the first end of the substrate being suspended on the first portion of the first support and the second end of the substrate being suspended on the first portion of the second support;
• removing a first portion of the substrate from the seed SiC layer by at least partially melting the substrate, the first portion being a continuous portion extending entirely from the first end to the second end along the first direction;
• forming a second SiC layer on a first surface of the seed SiC layer, the second SiC layer entirely covering the first surface, the forming the second SiC layer including:
• generating a first stress in the second SiC layer by introducing into the reaction chamber a precursor in gaseous phase of a first dopant having a first electrical conductivity;
• and
• generating a second stress in the second SiC layer that is opposite to the first stress by introducing into the reaction chamber a precursor in gaseous phase of a second dopant having a second electrical conductivity opposite to the first electrical conductivity;
• and
• removing a second portion of the substrate from the first SiC layer, the second portion being a residual portion remaining after removal of the first portion, completely by etching from the first SiC layer.