US 12,696,528 B2Granted

Semiconductor devices

AssigneeSamsung Electronics Co., Ltd.

InventorsDongjin Lee, Junhee Lim, Kangoh Yun, Sohyun Lee

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Abstract

A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.

Claims17

Dependent claims

A semiconductor device, comprising:

a substrate including a first region and a second region;
a first isolation structure extending through an upper portion of the first region of the substrate, the first isolation structure defining a first active region;
an impurity region under the first isolation structure in the substrate;
a first gate structure on the first region of the substrate, the first gate structure having a first thickness in a vertical direction perpendicular to an upper surface of the substrate;
a first source/drain region at an upper portion of the first active region adjacent to the first gate structure;
a second isolation structure extending through an upper portion of the second region of the substrate, the second isolation structure defining a second active region, and the second isolation structure having a void therein;
a second gate structure on the second region of the substrate, the second gate structure having a second thickness in the vertical direction that is less than the first thickness;
and
a second source/drain region at an upper portion of the second active region adjacent to the second gate structure,
wherein the first isolation structure includes:
an upper isolation pattern structure including:
a first isolation pattern;
and
a second isolation pattern covering a sidewall of the first isolation pattern, the second isolation pattern including an oxide;
and
a lower isolation pattern under and contacting the upper isolation pattern structure, a sidewall of the lower isolation pattern contacting the substrate, a width of the lower isolation pattern being greater than a width of a bottom of the upper isolation pattern structure, and
wherein a width of the impurity region is less than a width of the first isolation structure.

14 more elements

A semiconductor device, comprising:

a substrate including a first region, a second region and a third region;
a first isolation structure extending through an upper portion of the first region of the substrate, the first isolation structure defining a first active region;
an impurity region under the first isolation structure in the substrate;
a first gate structure on the first region of the substrate, the first gate structure having a first thickness in a vertical direction perpendicular to an upper surface of the substrate;
a first source/drain region at an upper portion of the first active region adjacent to the first gate structure;
a second isolation structure extending through an upper portion of the second region of the substrate, the second isolation structure defining a second active region, and the second isolation structure having a void therein;
a second gate structure on the second region of the substrate, the second gate structure having a second thickness in the vertical direction that is less than the first thickness;
a second source/drain region at an upper portion of the second active region adjacent to the second gate structure;
a third isolation structure extending through an upper portion of the third region of the substrate, the third isolation structure defining a third active region, and the third isolation structure having a seam therein;
a third gate structure on the third region of the substrate, the third gate structure having a third thickness in the vertical direction that is less than the second thickness;
and
a third source/drain region at an upper portion of the third active region adjacent to the third gate structure,
wherein the first isolation structure includes:
an upper isolation pattern structure;
and
a lower isolation pattern under and contacting the upper isolation pattern structure, a sidewall of the lower isolation pattern contacting the substrate, a width of the lower isolation pattern being greater than a width of a bottom of the upper isolation pattern structure, and
wherein a width of the impurity region is less than a width of the first isolation structure.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/133,977Filed 12 Apr 2023
Priority: KR 10-2022-007191914 Jun 2022
Published: US 2023/0402454 A114 Dec 2023
Granted: 28 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/8314
Of only insulated-gate FETs [IGFET]: the IGFETs characterised by having gate insulating layers with different properties