CMOS well regions with high dopant activation level and reduced extended defects
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Fan Chen, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
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Abstract
A method of fabricating an integrated circuit (IC) is provided. The method includes the following steps: providing a substrate; forming a p-well region in the substrate; forming an n-well region in the substrate; conducting a microwave annealing at a first temperature; conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature; and fabricating a plurality of field-effect transistors (FETs) in the p-well region and the n-well region.
Claims19
A method of fabricating an integrated circuit (IC), the method comprising:
- providing a substrate;
- forming a p-well region in the substrate using a first ion implantation process;
- forming an n-well region in the substrate using a second ion implantation process;
- conducting, after the first ion implantation process and the second ion implantation process, a microwave annealing at a first temperature, wherein the microwave annealing is conducted at the first temperature to recover point defects created during the first and second ion implantation processes;
- conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature, wherein the supplemental annealing is a non-microwave annealing, and wherein the supplemental annealing is conducted at the second temperature to activate dopants in the p-well region and the n-well region while avoiding formation of extended defects;
- and
- fabricating a plurality of field-effect transistors (FETs) in the p-well region and the n-well region.
A method of fabricating field-effect transistors (FETs), the method comprising:
- providing a substrate;
- forming a p-well region in the substrate using a first ion implantation process;
- forming an n-well region in the substrate using a second ion implantation process;
- conducting, after the first ion implantation process and the second ion implantation process, a microwave annealing at a first temperature, wherein the microwave annealing is conducted at the first temperature to recover point defects created during the first and second ion implantation processes;
- conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature, wherein the supplemental annealing is a non-microwave annealing, and wherein the supplemental annealing is conducted at the second temperature to activate dopants in the p-well region and the n-well region while avoiding formation of extended defects;
- forming a plurality of fin structures over the p-well region and the n-well region;
- forming a plurality of source regions and a plurality of drain regions of the plurality of fin structures;
- and
- forming a plurality of gate structures over the plurality of fin structures.
An integrated annealing system, comprising:
- a microwave annealing system configured to anneal a p-well region and an n-well region formed in a substrate on a wafer using a microwave annealing at a first temperature;
- a supplemental annealing system cascaded with the microwave annealing system and configured to anneal the p-well region and the n-well region formed in the substrate using a supplemental annealing at a second temperature higher than the first temperature, wherein the supplemental annealing is a non-microwave annealing, and wherein the microwave annealing system and the supplemental annealing system are located in close proximity in a housing;
- and
- a transfer robot located between the microwave annealing system and the supplemental annealing system and configured to transfer the wafer from the microwave annealing system to the supplemental annealing system.
Dependencies are inferred from the claim text.