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US 12,696,494 B2Granted
Method for forming transistor structure with a vertically grown source and drain
AssigneeInvention And Collaboration Laboratory Pte. Ltd.
InventorsChao-Chun Lu, Li-Ping Huang, Ming-Hong Kuo
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Abstract
A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.
Claims9
A method for forming a transistor structure comprising:
- preparing a substrate with an original surface;
- using a hard mask layer to form a gate recess;
- forming of a channel region comprising:
- depositing a doped semiconductor layer in the gate recess;
- thermal annealing the doped semiconductor layer to form the channel region underneath the gate recess;
- and
- forming a gate dielectric layer in the gate recess;
- forming a gate conductive region in the gate recess, wherein at least a portion of the gate conductive region is disposed below the original surface;
- and a bottom wall and sidewalls of the gate conductive region are surrounded by the gate dielectric layer;
- and
- forming a first conductive region after the forming of the gate conductive region, wherein a bottom wall of the first conductive region is aligned with a top wall of the gate conductive region.
8 more elements
A method for forming a transistor structure comprising:
- preparing a substrate with an original surface;
- using a nitride hard mask layer to form a gate recess for the gate conductive region;
- forming of a channel region comprising:
- depositing a p-type doped poly-silicon plug or oxide in the gate recess;
- and
- thermal annealing the p-type doped poly-silicon plug or oxide to form the channel region underneath the gate recess;
- forming a gate dielectric layer in the gate recess;
- forming a gate conductive region in the gate recess, wherein at least a portion of the gate conductive region is disposed below the original surface;
- and a bottom wall and sidewalls of the gate conductive region are surrounded by the gate dielectric layer;
- and
- forming a first conductive region after the forming of the gate conductive region, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.
8 more elements
A method for forming a transistor structure comprising:
- preparing a substrate with an original surface;
- forming a gate conductive region, wherein at least a portion of the gate conductive region is disposed below the original surface;
- and a bottom wall and sidewalls of the gate conductive region are surrounded by a gate dielectric layer, wherein the forming of the gate conductive region comprises:
- using a first hard mask layer to form a gate recess for the gate conductive region;
- forming a channel region comprising:
- depositing a doped semiconductor layer in the gate recess;
- and
- thermal annealing the doped semiconductor layer to form the channel region underneath the gate recess;
- forming the gate dielectric layer in the gate recess;
- and
- forming the gate conductive region in the gate recess;
- depositing a second hard mask layer over the gate conductive region;
- removing the first hard mask to reveal portion of the original surface of the substrate and etching down the revealed original surface to form a first recess;
- and
- forming a first conductive region by a selective growth process based on the first recess, wherein a bottom wall of the first conductive region is aligned with a top wall of the gate conductive region.
12 more elements
A method for forming a transistor structure comprising:
- preparing a substrate with an original surface;
- using a hard mask oxide layer to form a gate recess for the gate conductive region;
- depositing a p-type doped poly-silicon plug or oxide in the gate recess;
- thermal annealing the p-type doped poly-silicon plug or oxide to form the channel region underneath the gate recess;
- forming a gate dielectric layer in the gate recess;
- forming a gate conductive region in the gate recess, wherein at least a portion of the gate conductive region is disposed below the original surface;
- and a bottom wall and sidewalls of the gate conductive region are surrounded by the gate dielectric layer;
- and
- forming a first conductive region after the forming of the gate conductive region, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.
6 more elements
Dependencies are inferred from the claim text.