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US 12,696,493 B2Granted
Booster circuit for semiconductor memory device
AssigneeKioxia Corporation
InventorsTakao Sueyama, Naohiro Matsukawa, Keiko Kaneda
Life of this patent
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Abstract
The semiconductor wiring has the N-well layer of the impurity layer in the P substrate formed in the region where the poly wiring and P substrate face each other, wherein the N-well layer is electrically floating, is not used as a circuit element, and does not input or output signals. The semiconductor wiring is used as a transmission path of a high voltage signal, and used for a wiring that transmits a write signal of information at the memory cell array of the semiconductor memory device.
Claims16
A memory device, comprising:
- a memory cell array having a plurality of memory cells each connected to a word line and a bit line;
- a booster circuit configured to supply a write voltage to the word line;
- and
- a semiconductor wiring provided in the booster circuit,
- wherein the semiconductor wiring includes:
- a first semiconductor region of a first conductivity type;
- a floating layer provided in the first semiconductor region, and including impurities of a second conductivity type;
- an insulating layer formed on at least an entire upper surface of the floating layer and an upper surface of the first semiconductor region around the floating layer;
- and
- at least one semiconductor wiring layer provided on the insulating layer, and facing the floating layer via the insulating layer, the semiconductor wiring layer having a capacitive coupling with the floating layer via the insulating layer,
- wherein the insulating layer directly faces the first semiconductor region and the floating layer.
8 more elements
Dependencies are inferred from the claim text.