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US 12,696,484 B2Granted
Back-end-of-line vertical-transport transistor
AssigneeInternational Business Machines Corporation
InventorsHeng Wu, Julien Frougier, Ruilong Xie, Chen Zhang
Life of this patent
Estimating the term…
Abstract
A semiconductor structure including a bottom source drain region arranged above front-end-of-line circuitry, a gate region disposed above and insulated from the bottom source drain region, a top source drain region disposed above and insulated from the gate region, and a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
Claims20
A semiconductor structure comprising:
- a bottom source drain region arranged above front-end-of-line circuitry;
- a gate region disposed above and insulated from the bottom source drain region;
- a top source drain region disposed above and insulated from the gate region;
- a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region;
- and
- a gate dielectric separating the gate region from the channel region, wherein the channel region wraps around and directly contacts a bottom surface, a sidewall, and a top surface of the gate dielectric.
3 more elements
A semiconductor structure comprising:
- two or more bottom source drain regions arranged above front-end-of-line circuitry and electrically isolated from one another;
- a single gate region disposed above and insulated from the two or more bottom source drain regions;
- a trench isolator between and physically separating a first portion of the single gate region from a second portion of the single gate region, wherein sidewalls of the trench isolator directly contact a sidewall of the first portion of the single gate region and a sidewall of the second portion of the single gate region;
- two or more top source drain regions disposed above and insulated from the single gate region and electrically isolated from one another;
- and
- two or more channel regions adjacent to the single gate region, each channel region extending vertically from a top surface of one of the two or more bottom source drain regions to a bottom surface of one of the two or more top source drain regions.
3 more elements
A semiconductor structure comprising:
- a bottom source drain region arranged above front-end-of-line circuitry;
- a single gate region disposed above and insulated from the bottom source drain region;
- a top source drain region disposed above and insulated from the single gate region;
- a channel region surrounding the single gate region, the channel region extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region;
- a bottom gate spacer directly below the single gate region insulating the single gate region from the bottom source drain region;
- and
- a top gate spacer above the single gate region insulating the single gate region from the top source drain region,
- wherein the bottom gate spacer, the single gate region, and the top gate spacer have substantially equal widths.
5 more elements
Dependencies are inferred from the claim text.