Matching circuit board and semiconductor device

A matching circuit board comprising:

• a first substrate that includes a first insulator, a first metal pattern provided on a main surface of the first insulator, and a plurality of first conductive vias provided at a peripheral edge of the first insulator;
• a second substrate provided to face a first surface of the first substrate, the second substrate including a second insulator, a second metal pattern provided on a main surface of the second insulator, and a plurality of second conductive vias provided at a peripheral edge of the second insulator;
• a third substrate provided to face a second surface opposite to the first surface of the first substrate, the third substrate including a third insulator and a third metal pattern provided on a main surface of the third insulator,
• wherein a first capacitor is constituted by the first metal pattern, the second insulator, and the second metal pattern, and a second capacitor is constituted by the first metal pattern, the first insulator, and the third metal pattern,
• wherein the second metal pattern is electrically connected to the third metal pattern through the plurality of second conductive vias and the plurality of first conductive vias, and
• wherein the first metal pattern is separated from the plurality of first conductive vias to be positioned inside the plurality of first conductive vias, and is configured to be insulated from the plurality of first conductive vias;
• a fourth substrate provided on the second substrate, the fourth substrate including a fourth insulator, a fourth metal pattern provided on a main surface of the fourth insulator, and a plurality of fourth conductive vias provided at a peripheral edge of the fourth insulator,
• wherein the fourth metal pattern is electrically connected to the first metal pattern, and the plurality of fourth conductive vias are electrically connected to at least one of the second metal pattern and the second conductive vias, and
• wherein the fourth metal pattern is separated from the plurality of fourth conductive vias to be positioned inside the plurality of fourth conductive vias, and is configured to be insulated from the plurality of fourth conductive vias;
• and
• a fifth substrate provided to face the second surface of the first substrate and comprising a fifth insulator, a fifth metal pattern provided on a main surface of the fifth insulator, and a plurality of fifth conductive vias provided at a peripheral edge of the fifth insulator,
• wherein the fifth metal pattern forms an inductor.