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US 12,695,540 B2Granted
Scheduling method for LDPC decoding
AssigneeNVIDIA Corporation
InventorsYanxiang Huang, James Delfeld
Life of this patent
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Abstract
Apparatuses, systems, and techniques to correct errors in information received from a plurality of fifth-generation new radio antennas. In at least one embodiment, codeword information is decoded by a plurality of variable (or vector) nodes and check nodes, where codewords and nodes are divided among processors to be performed in parallel.
Claims34
One or more processors comprising:
- circuitry to perform error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
A system comprising:
- one or more processors to be configured to perform error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:
- perform error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
A method, comprising:
- performing error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
Dependencies are inferred from the claim text.