Receiver circuit and optical receiver circuit

A receiver circuit comprising:

• a first input node;
• a second input node;
• a constant current circuit that includes a first transistor and a second transistor, wherein the first input node is connected to a collector of the first transistor, and the second input node is connected to a collector of the second transistor;
• a DC voltage node;
• a current splitter circuit that includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein an emitter of the third transistor and an emitter of the fourth transistor are connected to the first input node, an emitter of the fifth transistor and an emitter of the sixth transistor are connected to the second input node, a collector of the fourth transistor and a collector of the fifth transistor are connected to the DC voltage node, a base of the third transistor and a base of the sixth transistor receive a first control signal, and a base of the fourth transistor and a base of the fifth transistor receive a second control signal;
• a load circuit that includes a first load resistor element and a second load resistor element, wherein the first load resistor element is connected between the DC voltage node and a collector of the third transistor, and the second load resistor element is connected between the DC voltage node and a collector of the sixth transistor;
• a differential transimpedance amplifier circuit that includes a seventh transistor, an eighth transistor, a ninth transistor, a first feedback resistor element, a second feedback resistor element, a third load resistor element, a fourth load resistor element, and a fifth load resistor element, wherein a base of the seventh transistor is connected to the first load resistor element, a base of the eighth transistor is connected to the second load resistor element, an emitter of the seventh transistor and an emitter of the eighth transistor are connected to a collector of the ninth transistor, the first feedback resistor element is connected between a collector and the base of the seventh transistor, the second feedback resistor element is connected between a collector and the base of the eighth transistor, the third load resistor element is connected between the fifth load resistor element and the seventh transistor, and the fourth load resistor element is connected between the fifth load resistor element and the eighth transistor;
• a first output terminal connected to the collector of the eighth transistor;
• a second output terminal connected to the collector of the seventh transistor;
• and
• a voltage regulator circuit that includes an FET connected between a power supply wire and the DC voltage node, and is configured to adjust a gate voltage of the FET so as to reduce at least a difference in respective average potentials of the collector of the third transistor, the collector of the sixth transistor, the collector of the seventh transistor, and the collector of the eighth transistor.