Low-latency data acquisition using sigma-delta modulators

A device, comprising:

• a processor;
• and
• memory coupled to the processor and storing instructions executable by the processor, the instructions configured to cause the processor to:
• receive, at time t, a first digital value based on a SINC filter operating on a digital bitstream representing an analog signal;
• receive a second digital value based on a cascade of integrators (COI) filter operating on the digital bitstream;
• determine a slope based on the first and second digital values;
• and
• predict a third digital value based on the slope and on a filter output value of the SINC filter or the COI filter, the third digital value representative of the analog signal at the time t.

A system, comprising:

• an analog-to-digital converter (ADC) configured to sample an analog signal and to provide a digital bitstream based on the analog signal, the ADC including a capacitor;
• a counter configured to:
• increment a counter value of the counter to exceed a threshold value based on a clock signal;
• and
• provide a reset signal responsive to the counter value of the counter exceeding the threshold value, the reset signal configured to adjust a voltage of the capacitor;
• and
• a controller coupled to the ADC and the counter, the controller configured to:
• provide the clock signal to the counter;
• receive a first digital value based on a SINC filter operating on the digital bitstream and a second digital value based on a cascade of integrators (COI) filter operating on the digital bitstream;
• determine a slope based on the first and second digital values;
• and
• predict a third digital value of the analog signal based on the slope.