Complementary 2(N)-bit redundancy for single event upset prevention

An integrated circuit comprising:

• an input node to receive a data value;
• a first data storage element having an input operably coupled to the input node, the first data storage element configured to store a complementary data value of the data value received at the input;
• a multi-bit data storage element having a first input operably coupled to the input node and a second input operably coupled to the input node, the multi-bit data storage element configured to store the data value and the complementary data value as separate values;
• and
• voter logic comprising:
• an output coupled to an output node of the integrated circuit;
• a first input of the voter logic operably coupled to an output of the first data storage element to receive a first logic value based on the complementary data value stored by the first data storage element;
• a second input of the voter logic coupled to a first output of the multi-bit data storage element to receive a second logic value based on the data value stored by the multi-bit data storage element;
• and
• a third input of the voter logic coupled to a second output of the multi-bit data storage element to receive a third logic value based on the complementary data value stored by the multi-bit data storage element,
• the voter logic configured to provide an output data value to the output node of the integrated circuit based on a set of respective logic values of at least two of the first logic value, second logic value, and third logic value.