US 12,695,380 B2Granted

Capacitor cross-coupled level shifter

AssigneeTexas Instruments Incorporated

InventorsKishore Peetala, Venkateswarlu Ramaswamy T

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Abstract

Described embodiments include a level-shifter circuit having first and second buffers. A second terminal of a first capacitor is coupled to the output of the first buffer. A second terminal of a second capacitor is coupled to the output of the second buffer. A first transistor is coupled between an input voltage terminal and the first terminal of the first capacitor, and has a first control terminal coupled to the first terminal of the second capacitor. A second transistor is coupled between the input voltage terminal and the first terminal of the second capacitor, and has a second control terminal coupled to the first terminal of the first capacitor. An overvoltage discharge circuit is configured to maintain a voltage imbalance between a first voltage across the first capacitor and a second voltage across the second capacitor to within a threshold voltage.

Claims24

Dependent claims

A level-shifter circuit comprising:

a first buffer having a first buffer input and a first buffer output, wherein the first buffer input is coupled to a first clock source;
a second buffer having a second buffer input and a second buffer output, wherein the second buffer input is coupled to a second clock source;
a first capacitor having first and second capacitor terminals, wherein the second capacitor terminal is coupled to the first buffer output;
a second capacitor having third and fourth capacitor terminals, wherein the fourth capacitor terminal is coupled to the second buffer output;
a first transistor coupled between an input voltage terminal and the first capacitor terminal and having a first control terminal, wherein the first control terminal is coupled to the third capacitor terminal;
a second transistor coupled between the input voltage terminal and the third capacitor terminal and having a second control terminal, wherein the second control terminal is coupled to the first capacitor terminal;
and
an overvoltage discharge circuit, wherein the overvoltage discharge circuit includes:
a third transistor coupled to the first capacitor terminal and having a third control terminal, wherein the third control terminal is coupled to the input voltage terminal;
a fourth transistor coupled between the third transistor and a ground terminal and having a fourth control terminal, wherein the fourth control terminal is coupled to the second clock source;
a fifth transistor coupled to the third capacitor terminal and having a fifth control terminal, wherein the fifth control terminal is coupled to the input voltage terminal;
and
a sixth transistor coupled between the fifth transistor and the ground terminal and having a sixth control terminal, wherein the sixth control terminal is coupled to the first clock source.

10 more elements

An apparatus comprising:

a first buffer having a first buffer input, a first buffer output and a first buffer power supply terminal, wherein the first buffer input is coupled to a first clock source, and the first buffer power supply terminal is configured to receive a buffer power supply;
a second buffer having a second buffer input, a second buffer output and a second buffer power supply terminal, wherein the second buffer input is coupled to a second clock source, and the second buffer power supply terminal is configured to receive the buffer power supply;
a first capacitor having first and second capacitor terminals, wherein the second capacitor terminal is coupled to the first buffer output;
a second capacitor having third and fourth capacitor terminals, wherein the fourth capacitor terminal is coupled to the second buffer output;
a first transistor coupled between an input voltage terminal and the first capacitor terminal and having a first control terminal, wherein the first control terminal is coupled to the third capacitor terminal;
a second transistor coupled between the input voltage terminal and the third capacitor terminal and having a second control terminal, wherein the second control terminal is coupled to the first capacitor terminal;
and
a circuit configured to reduce a voltage imbalance between a first voltage across the first capacitor and a second voltage across the second capacitor, wherein the circuit includes:
a third transistor coupled between the input voltage terminal and the first capacitor terminal and having a third control terminal, wherein the third control terminal is coupled to a bias voltage terminal;
a fourth transistor coupled between the bias voltage terminal and a ground terminal and having a fourth control terminal, wherein the fourth control terminal is coupled to the buffer power supply;
and
a fifth transistor coupled between the input voltage terminal and the third capacitor terminal and having a fifth control terminal, wherein the fifth control terminal is coupled to the bias voltage terminal.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/340,128Filed 23 Jun 2023
Priority: IN 20234103399615 May 2023
Published: US 2024/0388294 A121 Nov 2024
Granted: 28 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H02M 3/07
Using resistors or capacitors, e.g. potential divider: using capacitors charged and discharged alternately by semiconductor devices with control…
H03K 19/01855
Interface arrangements: synchronous, i.e. using clock signals
G05F 1/46
Regulating voltage or current: wherein the variable actually regulated by the final control device is DC
H02M 3/073
Using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps: charge pumps of the…