Memory device including repair circuit and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsWonyoung Jang, Taewon Kim, Sanghee Kang, Taeyun Kim
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Abstract
A memory device including a repair circuit and an operating method of the memory device are provided. The operating method includes outputting a signal representing a pre-decoded faulty row address based on predecoding a faulty row address, outputting a signal representing a pre-decoded row address based on predecoding a row address, outputting hit signals based on comparing a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address, outputting a repair enable signal based on the hit signals, and performing a row repair operation based on the repair enable signal.
Claims20
An operating method of a memory device, the operating method comprising:
- outputting, using a pre-decoder circuit, a signal representing a pre-decoded faulty row address based on predecoding a faulty row address;
- outputting, using the pre-decoder circuit, a signal representing a pre-decoded row address based on predecoding a row address;
- outputting hit signals based on comparing a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address;
- outputting a repair enable signal based on the hit signals;
- and
- performing a row repair operation based on the repair enable signal.
A memory device comprising:
- a memory cell array including a redundancy memory cell;
- and
- a repair circuit configured to perform a row repair operation by replacing a faulty row address with a redundancy row address, based on a repair enable signal,
- wherein the repair circuit comprises:
- a first register configured to store the faulty row address;
- a second register configured to store a row address;
- and
- a repair control circuit, and
- wherein the repair control circuit comprises:
- a pre-decoder circuit configured to predecode the faulty row address and output a signal that represents a pre-decoded faulty row address, and predecode the row address and output a signal that represents a pre-decoded row address;
- a comparison circuit configured to compare a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address and output hit signals based on a result of the comparison;
- and
- a combinational logic circuit configured to output the repair enable signal based on the hit signals.
A memory system comprising:
- a host device configured to transmit a command for a repair operation;
- and
- a memory device configured to perform the repair operation in response to the command,
- wherein the memory device includes a repair control circuit configured to:
- predecode, using a pre-decoder circuit of the repair control circuit, a faulty row address and output a signal that represents a pre-decoded faulty row address,
- predecode, using the pre-decoder circuit, a row address and output a signal that represents a pre-decoded row address,
- compare a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address and output hit signals based on a result of the comparison, and
- output a repair enable signal based on the hit signals.
Dependencies are inferred from the claim text.