Back to results
US 12,694,943 B2Granted
Non-volatile memory with leak tests
AssigneeSanDisk Technologies LLC
InventorsXuan Tian, Liang Li, Deepanshu Dutta
Life of this patent
Estimating the term…
Abstract
A non-volatile memory is configured to perform multiple leak tests integrated into a pre-erase process for a set (e.g., block) of non-volatile memory cells after the set of non-volatile memory cells have received programming. An inference circuit is configured to use results of the leak tests with a pre-trained model to predict whether the set of non-volatile memory cells will fail.
Claims20
A non-volatile storage apparatus, comprising:
- a non-volatile memory structure comprising a first set of non-volatile memory cells and signal lines connected to the first set of non-volatile memory cells;
- and
- a control circuit connected to the non-volatile memory structure and configured to program and erase the first set of non-volatile memory cells, the control circuit comprises an inference circuit, the control circuit is configured to perform multiple leak tests for the signal lines, the multiple leak tests are integrated into a pre-erase process for the first set of non-volatile memory cells after the first set of non-volatile memory cells have received programming, the inference circuit is configured to use results of the leak tests with a model to predict whether the first set of non-volatile memory cells will fail, the control circuit is further configured to perform an erase process for the first set of non-volatile memory cells including applying one or more erase voltage pulses to the first set of non-volatile memory cells while using the inference circuit to predict whether the first set of non-volatile memory cells will fail.
A method, comprising:
- performing multiple different leak tests for a set of signal lines connected to a first set of non-volatile memory cells, including measuring operational data during each of the leak tests;
- using an inference engine with a pre-trained model and the operational data measured during each of the leak tests to predict whether the first set of non-volatile memory cells will fail;
- while using the inference engine to predict whether the first set of non-volatile memory cells will fail, performing an erase process including applying one or more erase voltage pulses to the first set of non-volatile memory cells and performing erase verify after at least a subset of the erase voltage pulses until the erase process is determined to have passed or failed;
- allowing the first set of non-volatile memory cells to store valid user data in response to determining that the erase process passed and the inference engine predicting that the first set of non-volatile memory cells will not fail;
- and
- preventing the first set of non-volatile memory cells from storing valid user data in response to determining that the erase process failed or the inference engine predicting that the first set of non-volatile memory cells will fail.
3 more elements
A non-volatile storage apparatus, comprising:
- a memory die assembly comprising:
- a non-volatile memory structure comprising a block of non-volatile memory cells arranged in NAND strings, data word lines connected to the block, source side select lines connected to the block, drain side select lines connected to the block and additional non-volatile memory cells storing a pre-trained model received pre-trained from a source external to the non-volatile storage apparatus;
- and
- control circuit connected to the non-volatile memory structure and configured to program and erase the block of non-volatile memory cells, the control circuit comprises an inference circuit positioned in the memory die assembly, the control circuit is configured to:
- perform leak tests for the data word lines by applying high voltages to some of the word lines and low voltages to other of the word lines and sensing a first set of one or more measurements indicative of current flowing,
- perform leak tests for the source side select lines by applying high voltages to source side select lines and low voltages to data word lines and sensing a second set of one or more measurements indicative of current flowing,
- perform leak tests for the drain side select lines by applying high voltages to drain side select lines and low voltages to data word lines and sensing a third set of one or more measurements indicative of current flowing,
- use the inference circuit with pre-trained model, the first set of one or more measurements indicative of current flowing, the second set of one or more measurements indicative of current flowing, and the third set of one or more measurements indicative of current flowing to predict whether the block will fail,
- perform an erase process on the block while using the inference circuit to predict whether the block will fail,
- add the block to a bad block pool in response to the inference circuit predicting that the block will fail or the erase process failing, and
- use the block to store new data in response to the inference circuit predicting that the block will not fail or the erase process succeeding.
8 more elements
Dependencies are inferred from the claim text.